文件列表:

EE256v02 (0, 2006-03-30)
EE256v02\BF561_AutomateOpenProjects.vbs (1722, 2005-02-01)
EE256v02\Core A (0, 2006-03-30)
EE256v02\Core A\ADV7183_reset.c (2045, 2005-02-01)
EE256v02\Core A\CoreA.dpj (7872, 2005-02-01)
EE256v02\Core A\CoreA.mak (8785, 2005-02-01)
EE256v02\Core A\Debug (0, 2006-03-30)
EE256v02\Core A\Debug\ADV7183_reset.doj (5576, 2005-02-01)
EE256v02\Core A\Debug\Init_DMA.doj (6344, 2005-02-01)
EE256v02\Core A\Debug\Init_FrameBufPtr.doj (1796, 2005-02-01)
EE256v02\Core A\Debug\Init_PPI.doj (4580, 2005-02-01)
EE256v02\Core A\Debug\Init_SDRAM.doj (4860, 2005-02-01)
EE256v02\Core A\Debug\Interrupt_Init.doj (5672, 2005-02-01)
EE256v02\Core A\Debug\Interrupt_Service.doj (5592, 2005-02-01)
EE256v02\Core A\Debug\main.doj (7460, 2005-02-01)
EE256v02\Core A\Debug\set_PLL.doj (5816, 2005-02-01)
EE256v02\Core A\DescriptorDMA_PPI.h (4868, 2004-08-24)
EE256v02\Core A\Init_DMA.c (2131, 2005-02-01)
EE256v02\Core A\Init_FrameBufPtr.ASM (1960, 2005-02-01)
EE256v02\Core A\Init_PPI.c (796, 2005-02-01)
EE256v02\Core A\Interrupt_Init.c (1237, 2005-02-01)
EE256v02\Core A\Interrupt_Service.c (1237, 2005-02-01)
EE256v02\Core A\main.c (1838, 2005-02-01)
EE256v02\Core A\main.h (1066, 2004-08-25)
EE256v02\Core A\YCbCrtoRGB.asm (6367, 2005-02-01)
EE256v02\Core B (0, 2006-03-30)
EE256v02\Core B\CoreB.dpj (9065, 2005-02-01)
EE256v02\Core B\CoreB.mak (9220, 2005-02-01)
EE256v02\Core B\Debug (0, 2006-03-30)
EE256v02\Core B\Debug\Decimate.doj (2488, 2005-02-01)
EE256v02\Core B\Debug\Init_DMA.doj (6440, 2005-02-01)
EE256v02\Core B\Debug\Init_FrameBufPtr.doj (1768, 2005-02-01)
EE256v02\Core B\Debug\Init_PF.doj (4568, 2005-02-01)
EE256v02\Core B\Debug\Init_PPI.doj (4716, 2005-02-01)
EE256v02\Core B\Debug\Init_Timers.doj (6536, 2005-02-01)
EE256v02\Core B\Debug\Interrupt_Init.doj (5420, 2005-02-01)
EE256v02\Core B\Debug\Interrupt_Service.doj (7644, 2005-02-01)
EE256v02\Core B\Debug\main.doj (9180, 2005-02-01)
EE256v02\Core B\Debug\set_PLL.doj (5816, 2005-02-01)
EE256v02\Core B\Debug\YCbCrtoRGB.doj (2132, 2005-02-01)
... ...

**************************************************************************************************** ADSP-BF561 EZ-KIT Example Code This file accompanies Rev 2 of the application note Using the ADSP-BF561 Blackfin Processor as a TFT-LCD Controller (EE-256) that can be found at http://www.analog.com/ee-notes. Analog Devices, Inc. Three Technology Way Norwood, MA 02062 Date Created: March 2006 ____________________________________________________________________________________________________ This example streams input from a video source to an output LCD display that uses a timing ASIC. In order to reduce cost and space, many LCDs remove the timing ASIC from the LCD module and require it externally. This particular type of LCD display was chosen for this application to demonstrate the ADSP-BF561 Blackfin Processor's capability to provide a glueless interface to such an LCD display, thus reducing the cost and space of providing an external timing ASIC. A video source is acquired frame-by-frame into SDRAM from the ADSP-BF561 Blackfin EZ-KIT Lite's onboard video decoder (ADV7183A). The frames are then processed and outputted to the LCD. This is a dual core project. Core A is simply used to receive the input frames (via DMA). No core processing is done on Core A. Core B processes the received frames and outputs to the LCD. Please see section III. to get familiar with the dual core project structure. ____________________________________________________________________________________________________ Application was done using ADSP-BF561 Blackfin silicon revision 0.3 ADSP-BF561 EZ-KIT Lite revision 1.3 VisualDSP++ release 3.5 ____________________________________________________________________________________________________ CONTENTS I. FUNCTIONAL DESCRIPTION II. OPERATION DESCRIPTION III. PROJECT STRUCTURE I. FUNCTIONAL DESCRIPTION Core A sets up Clock frequencies, SDRAM controller, the Video Decoder, and PPI0 to perform the video acquisiton in ITU-656 mode. Frames are streamed into SDRAM (in a circular fashion to 2 buffered frames at a time). Core B sets up PPI1 to perform video output. It processes the incoming video frame in memory from Core A, and starts the transfers to the display. GP output mode is used to interface to the LCD. The Video Decoder is kept in its power up configuration. No other configuration is done. If you need to change settings, you may do so by adding code for I2C routines. II. OPERATION DESCRIPTION - Load the "BF561_AutomateOpenProjects.vbs" script in VDSP++ via File -> Load Script, or follow the instructions in section III. - Under the "Project" tab, select "Build Project" (program is then loaded automatically into DSP). - Connect a video NTSC/PAL CVBS source to the bottom right connector of J6 (video in/out jack) - Connect an LCD display using the diagrams and pin interface provided in the Appendix of the EE-256 - Dipswitch SW5: set #1 and #4 to "off", all others to on - Dipswitch SW2: set #6 to on, all others to off - Dipswitch SW3: set #1,4 to "off", #2,3 to on - Dipswitch SW4: set all to "off" - Run the executables by pressing "multiprocessor run" (CTRL-F5) on the toolbar. DO NOT use the single core (F5) button. You should see a copy of the input video on the LCD screen. - The main header file "system.h" contains #define statements for most of the system settings (clock frequencies etc) III. PROJECT STRUCTURE This is a dual core project. It consists of a main project - containing only system defines and linker settings- ".\LCD.dpj" and four sub-projects - containing the source code - ".\coreA\coreA.dpj" ( code exclusive to core A, in L1 memory) ".\coreB\coreB.dpj" ( code exclusive to core B, in L1 memory) ".\Shared Memory L2\L2_SRAM.dpj" ( code that is shared between the cores, in on-chip L2 memory) ".\Shared Memory L3\L3_SDRAM.dpj" ( code that is shared between the cores, in off-chip L3 memory, SDRAM) Either load the .vbs script describe in section II, or follow this procedure to open and compile the project: - open the main (LCD.dpj) project (Project -> open) - with the same menu item, open the coreA, coreB, L2_SRAM and L3_SDRAM projects. - Right click on the main project. Click the "set as active project" to activate the main project. - In the project menu, select "project dependencies". You will see an empty check box for each of the four sub-projects. Check all four boxes. - Re-build the project.

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