verilog.HDL.examples

所属分类VHDL/FPGA/Verilog
开发工具:Visual C++
文件大小:184KB
下载次数:3017
上传日期:2007-05-03 04:54:46
上 传 者张驰
说明:  许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等
(many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.)

文件列表:[举报垃圾]
verilog实例
...........\ADC_16bit.v
...........\adder_8bit.v
...........\adder_8bit_2.v
...........\ALL.V
...........\binarytogray.v
...........\cla_8bits.v
...........\COMPARE.V
...........\dds.v.txt
...........\DECODER1.V
...........\decoder3x8.v
...........\div16.v.txt
...........\encoder8x3.v
...........\encoder8x3_2.v
...........\FIFO.V
...........\fifo.v.txt
...........\fifo_16x16.v
...........\FIFO_2.V
...........\framer.v.txt
...........\frequency5x2.v
...........\full_adder_1.v
...........\full_adder_2.v
...........\gencrc.v.txt
...........\half_adder_1.v
...........\half_adder_2.v
...........\half_adder_3.v
...........\lead_8bits_adder.v
...........\lead_8bits_adder2.v
...........\MUL16.V
...........\mult16.v.txt
...........\multi_select_1.v
...........\mult_piped_8x8.v
...........\mult_select.v
...........\MUX8X8.V
...........\myrand.c.txt
...........\nco.v.txt
...........\onehot.v.txt
...........\pic.v.txt
...........\PLI.TAR
...........\RISC8.ZIP
...........\sequence_dectect.v
...........\SHIFTER.V
...........\string.v.txt
...........\SYNTHPIC.ZIP
...........\TEST.V
...........\testing.v.txt
...........\test_cla_8bits.v
...........\wpulse.v.txt

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