verilog.HDL.examples

所属分类:VHDL/FPGA/Verilog
开发工具:Visual C++
文件大小:184KB
下载次数:3029
上传日期:2007-05-03 04:54:46
上 传 者drkshcn
说明:  许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等
(many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.)

文件列表:
verilog实例\ADC_16bit.v (3898, 2005-09-02)
verilog实例\ALL.V (309, 2005-09-02)
verilog实例\COMPARE.V (118, 2005-09-02)
verilog实例\DECODER1.V (97, 2005-09-02)
verilog实例\FIFO.V (2970, 2005-09-02)
verilog实例\FIFO_2.V (6616, 2005-09-02)
verilog实例\MUL16.V (1461, 2005-09-02)
verilog实例\MUX8X8.V (391, 2005-09-02)
verilog实例\PLI.TAR (19456, 2005-09-02)
verilog实例\RISC8.ZIP (81282, 2005-09-02)
verilog实例\SHIFTER.V (332, 2005-09-02)
verilog实例\SYNTHPIC.ZIP (48357, 2005-09-02)
verilog实例\TEST.V (1055, 2005-09-02)
verilog实例\adder_8bit.v (241, 2005-09-02)
verilog实例\adder_8bit_2.v (1029, 2005-09-02)
verilog实例\binarytogray.v (527, 2005-09-02)
verilog实例\cla_8bits.v (1559, 2005-09-02)
verilog实例\dds.v.txt (2382, 2005-09-02)
verilog实例\decoder3x8.v (589, 2005-09-02)
verilog实例\div16.v.txt (7535, 2005-09-02)
verilog实例\encoder8x3.v (184, 2005-09-02)
verilog实例\encoder8x3_2.v (311, 2005-09-02)
verilog实例\fifo.v.txt (6616, 2005-09-02)
verilog实例\fifo_16x16.v (1351, 2005-09-02)
verilog实例\framer.v.txt (8500, 2005-09-02)
verilog实例\frequency5x2.v (1953, 2005-09-02)
verilog实例\full_adder_1.v (308, 2005-09-02)
verilog实例\full_adder_2.v (216, 2005-09-02)
verilog实例\gencrc.v.txt (9790, 2005-09-02)
verilog实例\half_adder_1.v (96, 2005-09-02)
verilog实例\half_adder_2.v (107, 2005-09-02)
verilog实例\half_adder_3.v (108, 2005-09-02)
verilog实例\lead_8bits_adder.v (1104, 2005-09-02)
verilog实例\lead_8bits_adder2.v (1022, 2005-09-02)
verilog实例\mult16.v.txt (3276, 2005-09-02)
verilog实例\mult_piped_8x8.v (1990, 2005-09-02)
verilog实例\mult_select.v (918, 2005-09-02)
verilog实例\multi_select_1.v (279, 2005-09-02)
verilog实例\myrand.c.txt (5401, 2005-09-02)
verilog实例\nco.v.txt (7416, 2005-09-02)
... ...

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