1_061026140305

所属分类:VHDL/FPGA/Verilog
开发工具:DOS
文件大小:200KB
下载次数:98
上传日期:2007-05-16 15:55:16
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说明:  基于FPGA的I2C总线模拟,采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.
(FPGA-based I2C bus simulation, using verilog HDL language.- Based on the FPGA I2C main line simulation, verilog uses the HDL language compilation.)

文件列表:
RD1006\Document\rd1006.pdf (204424, 2004-09-28)
RD1006\Document (0, 2004-09-28)
RD1006\Source\i2c.v (6629, 2004-09-28)
RD1006\Source\i2c_clk.v (2940, 2004-09-28)
RD1006\Source\i2c_rreg.v (3219, 2004-09-28)
RD1006\Source\i2c_st.v (9030, 2004-09-28)
RD1006\Source\i2c_tbuf.v (2528, 2004-09-28)
RD1006\Source\i2c_wreg.v (4579, 2004-09-28)
RD1006\Source\transcript (441, 2004-11-01)
RD1006\Source (0, 2005-06-07)
RD1006\TestFixture\clk_rst.v (3945, 2004-09-28)
RD1006\TestFixture\i2c_slave.v (24001, 2004-09-28)
RD1006\TestFixture\i2c_tb.v (2853, 2004-09-28)
RD1006\TestFixture\micro.v (5514, 2004-09-28)
RD1006\TestFixture (0, 2005-06-07)
RD1006 (0, 2005-06-07)

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