fulleradder
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：30KB
下载次数：51
上传日期：2007-06-15 09:35:02
上 传 者：
liuxj5502
说明： 本程序以Modelsim为开发平台，采用VHDL为开发语言，实现了简单的全加器．适合初学Modelsim的同行
(Modelsim the procedures for the development of a platform for the development of VHDL language, achieving a simple full adder. Suitable for a novice counterparts Modelsim)
文件列表:
FullAdder.vhd.bak (746, 2007-06-10)
top.vhd (762, 2007-06-10)
top.vhd.bak (2, 2007-06-10)
vsim.wlf (40960, 2007-06-10)
wave.do (796, 2007-06-10)
work\full_adder\behavioral.dat (511, 2007-06-10)
work\full_adder\_primary.dat (225, 2007-06-10)
work\_info (877, 2007-06-10)
work\_opt\work_full_adder_behavioral.asm (3467, 2007-06-10)
work\_opt\work__info (877, 2007-06-10)
work\_opt\_deps (203, 2007-06-10)
work\_opt\__model_tech_.._ieee__info (7609, 2007-06-10)
work\_opt\__model_tech_.._std__info (682, 2007-06-10)
FullAdder.mpf (30254, 2007-06-10)
FullAdder.vhd (746, 2007-06-10)
FullAdder1.mpf (30488, 2007-06-10)
FullAdder1.cr.mti (431, 2007-06-10)
FullAdder.cr.mti (545, 2007-06-10)
work\full_adder (0, 2007-06-10)
work\_opt (0, 2007-06-10)
work (0, 2007-06-10)
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