CPUNEW
所属分类：VHDL/FPGA/Verilog
开发工具：matlab
文件大小：49KB
下载次数：11
上传日期：2007-07-12 11:01:40
上 传 者：
lyz1030
说明： MODELSIM开发的模拟CPU，用VHDL语言描述，采用累加结构
(ModelSim simulation developed CPU, using VHDL language description of the structure of the use of cumulative)
文件列表:
CPUNEW\cpu.do (74, 2007-07-11)
CPUNEW\cpu.do.bak (68, 2007-07-11)
CPUNEW\cpu.vhd (6668, 2007-07-11)
CPUNEW\cpu.vhd.bak (2, 2007-07-11)
CPUNEW\cpunew.cr.mti (2, 2007-07-11)
CPUNEW\cpunew.mpf (19862, 2007-07-11)
CPUNEW\CPUNEW2.cr.mti (1143, 2007-07-11)
CPUNEW\CPUNEW2.mpf (21082, 2007-07-11)
CPUNEW\raw.vhd (1274, 2007-07-11)
CPUNEW\raw.vhd.bak (1274, 2007-07-11)
CPUNEW\stimulus.do (317, 2007-07-08)
CPUNEW\top.vhd (1429, 2007-07-11)
CPUNEW\top.vhd.bak (1429, 2007-07-11)
CPUNEW\transcript (1610, 2007-07-11)
CPUNEW\vsim.wlf (32768, 2007-07-11)
CPUNEW\work\cpu.do (68, 2007-07-11)
CPUNEW\work\cpu.do.bak (65, 2007-07-11)
CPUNEW\work\cpu.vhd (6668, 2007-07-11)
CPUNEW\work\cpu.vhd.bak (2, 2007-07-11)
CPUNEW\work\cpunew.cr.mti (2, 2007-07-11)
CPUNEW\work\cpunew.mpf (19907, 2007-07-11)
CPUNEW\work\raw.vhd (1274, 2007-07-11)
CPUNEW\work\raw.vhd.bak (1274, 2007-07-11)
CPUNEW\work\stimulus.do (317, 2007-07-08)
CPUNEW\work\top.vhd (758, 2007-07-11)
CPUNEW\work\top.vhd.bak (758, 2007-07-11)
CPUNEW\work\transcript (451, 2007-07-11)
CPUNEW\work\_info (2362, 2007-07-11)
CPUNEW\work\top\toparch.asm (6353, 2007-07-11)
CPUNEW\work\top\toparch.dat (928, 2007-07-11)
CPUNEW\work\top\_primary.dat (484, 2007-07-11)
CPUNEW\work\ram\ramarch.asm (7195, 2007-07-11)
CPUNEW\work\ram\ramarch.dat (795, 2007-07-11)
CPUNEW\work\ram\_primary.dat (341, 2007-07-11)
CPUNEW\work\cpu\cpuarch.asm (27123, 2007-07-11)
CPUNEW\work\cpu\cpuarch.dat (4097, 2007-07-11)
CPUNEW\work\cpu\_primary.dat (517, 2007-07-11)
CPUNEW\work\commonconstants\_primary.dat (129, 2007-07-11)
CPUNEW\work\commonconstants\_vhdl.asm (496, 2007-07-11)
CPUNEW\work\top (0, 2007-07-11)
... ...
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