FIFO_Buffer
所属分类：VHDL/FPGA/Verilog
开发工具：Windows_Unix
文件大小：68KB
下载次数：85
上传日期：2007-07-12 23:54:24
上 传 者：
eric8868
说明： 同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序，erilog编写~具有较强的参考价值~
(Synchronous and asynchronous sequential circuits fifo source and test procedures. Rar- fifo source, erilog prepared ~ has a strong reference to the value of ~)
文件列表:
FIFO_Asyn\FIFO_Buffer.v (2209, 2007-07-02)
FIFO_Asyn\FIFO_Buffer.v.bak (2205, 2007-07-02)
FIFO_Asyn\my_FIFO_Asyn.cr.mti (1149, 2007-07-02)
FIFO_Asyn\my_FIFO_Asyn.mpf (25611, 2007-07-02)
FIFO_Asyn\Ser_Par_Conv_32.v (1103, 2007-07-02)
FIFO_Asyn\t_FIFO_Clock_Domain_Synch.v (3043, 2007-07-02)
FIFO_Asyn\t_FIFO_Clock_Domain_Synch.v.bak (3022, 2007-07-02)
FIFO_Asyn\vsim.wlf (40960, 2007-07-02)
FIFO_Asyn\work\@f@i@f@o_@buffer\verilog.asm (21535, 2007-07-02)
FIFO_Asyn\work\@f@i@f@o_@buffer\_primary.dat (1489, 2007-07-02)
FIFO_Asyn\work\@f@i@f@o_@buffer\_primary.vhd (848, 2007-07-02)
FIFO_Asyn\work\@f@i@f@o_@buffer (0, 2007-07-02)
FIFO_Asyn\work\@ser_@par_@conv_32\verilog.asm (10212, 2007-07-02)
FIFO_Asyn\work\@ser_@par_@conv_32\_primary.dat (895, 2007-07-02)
FIFO_Asyn\work\@ser_@par_@conv_32\_primary.vhd (483, 2007-07-02)
FIFO_Asyn\work\@ser_@par_@conv_32 (0, 2007-07-02)
FIFO_Asyn\work\t_@f@i@f@o_@clock_@domain_@synch\verilog.asm (26493, 2007-07-02)
FIFO_Asyn\work\t_@f@i@f@o_@clock_@domain_@synch\_primary.dat (2085, 2007-07-02)
FIFO_Asyn\work\t_@f@i@f@o_@clock_@domain_@synch\_primary.vhd (250, 2007-07-02)
FIFO_Asyn\work\t_@f@i@f@o_@clock_@domain_@synch (0, 2007-07-02)
FIFO_Asyn\work\write_synchronizer\verilog.asm (3754, 2007-07-02)
FIFO_Asyn\work\write_synchronizer\_primary.dat (304, 2007-07-02)
FIFO_Asyn\work\write_synchronizer\_primary.vhd (284, 2007-07-02)
FIFO_Asyn\work\write_synchronizer (0, 2007-07-02)
FIFO_Asyn\work\_info (1160, 2007-07-02)
FIFO_Asyn\work (0, 2007-07-02)
FIFO_Asyn\write_synchronizer.v (412, 2007-06-29)
FIFO_Asyn (0, 2007-07-02)
FIFO_Syn\FIFO_Buffer.v (2069, 2007-06-29)
FIFO_Syn\FIFO_Syn.cr.mti (529, 2007-07-02)
FIFO_Syn\FIFO_Syn.mpf (24576, 2007-07-02)
FIFO_Syn\t_FIFO_Buffer.v (1663, 2007-06-29)
FIFO_Syn\vsim.wlf (40960, 2007-07-02)
FIFO_Syn\work\@f@i@f@o_@buffer\verilog.asm (21535, 2007-07-02)
FIFO_Syn\work\@f@i@f@o_@buffer\_primary.dat (1485, 2007-07-02)
FIFO_Syn\work\@f@i@f@o_@buffer\_primary.vhd (848, 2007-07-02)
FIFO_Syn\work\@f@i@f@o_@buffer (0, 2007-07-02)
FIFO_Syn\work\t_@f@i@f@o_@buffer\verilog.asm (17975, 2007-07-02)
FIFO_Syn\work\t_@f@i@f@o_@buffer\_primary.dat (1406, 2007-07-02)
FIFO_Syn\work\t_@f@i@f@o_@buffer\_primary.vhd (226, 2007-07-02)
... ...
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