FIFO_Syn

所属分类:VHDL/FPGA/Verilog
开发工具:Others
文件大小:25KB
下载次数:104
上传日期:2007-07-13 20:19:28
上 传 者ssw1983
说明:  同步FIFO功能,verilog语言描述,通过了modelsim 6.0 仿真,Quartue综合
(Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated)

文件列表:
FIFO_Syn\FIFO_Buffer.v (2069, 2007-06-29)
FIFO_Syn\FIFO_Syn.cr.mti (529, 2007-07-02)
FIFO_Syn\FIFO_Syn.mpf (24576, 2007-07-02)
FIFO_Syn\t_FIFO_Buffer.v (1663, 2007-06-29)
FIFO_Syn\vsim.wlf (40960, 2007-07-02)
FIFO_Syn\work\@f@i@f@o_@buffer\verilog.asm (21535, 2007-07-02)
FIFO_Syn\work\@f@i@f@o_@buffer\_primary.dat (1485, 2007-07-02)
FIFO_Syn\work\@f@i@f@o_@buffer\_primary.vhd (848, 2007-07-02)
FIFO_Syn\work\@f@i@f@o_@buffer (0, 2007-07-02)
FIFO_Syn\work\t_@f@i@f@o_@buffer\verilog.asm (17975, 2007-07-02)
FIFO_Syn\work\t_@f@i@f@o_@buffer\_primary.dat (1406, 2007-07-02)
FIFO_Syn\work\t_@f@i@f@o_@buffer\_primary.vhd (226, 2007-07-02)
FIFO_Syn\work\t_@f@i@f@o_@buffer (0, 2007-07-02)
FIFO_Syn\work\_info (611, 2007-07-02)
FIFO_Syn\work (0, 2007-07-02)
FIFO_Syn (0, 2007-07-02)

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