chuangbingzhuanhuan
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：24KB
下载次数：34
上传日期：2007-08-06 21:22:54
上 传 者：
xalg
说明： 一个用verilog写的串行传输到并行传输的程序，在quaters下编的
(Using Verilog to write a serial transmission to the parallel transmission of the procedure, under the quaters)
文件列表:
stop (0, 2007-07-01)
stop\s_to_p_tb.v (979, 2007-07-02)
stop\work (0, 2007-07-01)
stop\work\_info (403, 2007-07-02)
stop\work\s_to_p (0, 2007-07-01)
stop\work\s_to_p\_primary.vhd (787, 2007-07-02)
stop\work\s_to_p\verilog.asm (16151, 2007-07-02)
stop\work\s_to_p\_primary.dat (1545, 2007-07-02)
stop\work\s_to_p_tb (0, 2007-07-01)
stop\work\s_to_p_tb\_primary.vhd (138, 2007-07-02)
stop\work\s_to_p_tb\verilog.asm (9567, 2007-07-02)
stop\work\s_to_p_tb\_primary.dat (940, 2007-07-02)
stop\s_to_p.v.bak (3674, 2007-07-02)
stop\s_to_p.cr.mti (471, 2007-07-02)
stop\s_to_p_tb.v.bak (979, 2007-07-02)
stop\vsim.wlf (32768, 2007-07-02)
stop\s_to_p.mpf (20447, 2007-07-02)
stop\s_to_p.v (3674, 2007-07-02)
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