maxbijiao
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：30KB
下载次数：28
上传日期：2007-08-06 21:25:18
上 传 者：
xalg
说明： 在quaters下写的比较数的大小输出，verilog语言写的，具有状态机和存储器
(Written in the quaters of the size of the comparator output, verilog language written with the state machine and memory)
文件列表:
ss (0, 2007-07-07)
ss\top_tb.v (578, 2007-07-07)
ss\data_hex4x4.txt (99, 2007-07-07)
ss\rom_wave_out.v (1017, 2007-07-07)
ss\lev.v (924, 2007-07-07)
ss\top.v (2795, 2007-07-07)
ss\max.v (915, 2007-07-07)
ss\vsim.wlf (32768, 2007-07-07)
ss\top.mpf (21857, 2007-07-07)
ss\top.cr.mti (1095, 2007-07-07)
ss\work (0, 2007-07-07)
ss\work\_info (872, 2007-07-07)
ss\work\lev (0, 2007-07-07)
ss\work\lev\_primary.vhd (335, 2007-07-07)
ss\work\lev\verilog.asm (4624, 2007-07-07)
ss\work\lev\_primary.dat (811, 2007-07-07)
ss\work\max (0, 2007-07-07)
ss\work\max\_primary.vhd (378, 2007-07-07)
ss\work\max\verilog.asm (4625, 2007-07-07)
ss\work\max\_primary.dat (619, 2007-07-07)
ss\work\rom_wave_out (0, 2007-07-07)
ss\work\rom_wave_out\_primary.vhd (353, 2007-07-07)
ss\work\rom_wave_out\verilog.asm (4515, 2007-07-07)
ss\work\rom_wave_out\_primary.dat (682, 2007-07-07)
ss\work\top (0, 2007-07-07)
ss\work\top\_primary.vhd (638, 2007-07-07)
ss\work\top\verilog.asm (13548, 2007-07-07)
ss\work\top\_primary.dat (1781, 2007-07-07)
ss\work\top_tb (0, 2007-07-07)
ss\work\top_tb\_primary.vhd (132, 2007-07-07)
ss\work\top_tb\verilog.asm (5680, 2007-07-07)
ss\work\top_tb\_primary.dat (580, 2007-07-07)
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