ddr_ctrl
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：27KB
下载次数：279
上传日期：2007-08-20 16:51:05
上 传 者：
jackyw
说明： verilog hdl coding DDR sdram control for fpga
(verilog hdl coding DDR sdram control for fpga)
文件列表:
ddr_ctrl\.svn\text-base\ddr_top.v.svn-base (9613, 2007-07-20)
ddr_ctrl\.svn\text-base\ddr_par.v.svn-base (9165, 2007-07-20)
ddr_ctrl\.svn\text-base\ddr_sig.v.svn-base (9107, 2007-07-20)
ddr_ctrl\.svn\text-base\ddr_ctrl.v.svn-base (15658, 2007-07-20)
ddr_ctrl\.svn\text-base\ddr_data.v.svn-base (12325, 2007-07-20)
ddr_ctrl\.svn\format (2, 2007-07-20)
ddr_ctrl\.svn\all-wcprops (686, 2007-07-20)
ddr_ctrl\.svn\entries (826, 2007-07-20)
ddr_ctrl\ddr_top.v (9613, 2007-07-20)
ddr_ctrl\ddr_par.v (9165, 2007-07-20)
ddr_ctrl\ddr_sig.v (9107, 2007-07-20)
ddr_ctrl\ddr_ctrl.v (15658, 2007-07-20)
ddr_ctrl\ddr_data.v (12325, 2007-07-20)
ddr_ctrl\.svn\tmp\text-base (0, 2007-08-07)
ddr_ctrl\.svn\tmp\prop-base (0, 2007-08-07)
ddr_ctrl\.svn\tmp\props (0, 2007-08-07)
ddr_ctrl\.svn\text-base (0, 2007-07-20)
ddr_ctrl\.svn\prop-base (0, 2007-07-20)
ddr_ctrl\.svn\props (0, 2007-07-20)
ddr_ctrl\.svn\tmp (0, 2007-08-07)
ddr_ctrl\.svn (0, 2007-07-20)
ddr_ctrl (0, 2007-07-20)
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