DE2_Default
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：3067KB
下载次数：113
上传日期：2007-09-06 09:07:09
上 传 者：
greatpeace
说明： DE2开发版的默认程序，verilog，里面对各个模块都进行了控制，而且程序非常规范，值得学习
(DE2 development version of the default proceedings, verilog, inside of each module have been controlled and standardized procedures, it is worth learning)
文件列表:
DE2_Default\AUDIO_DAC.v (8754, 2005-08-15)
DE2_Default\cmp_state.ini (2, 2006-08-10)
DE2_Default\db\altsyncram_8en1.tdf (132086, 2006-07-07)
DE2_Default\db\altsyncram_e3f1.tdf (2511, 2006-07-07)
DE2_Default\db\altsyncram_ekk.tdf (14807, 2006-07-07)
DE2_Default\db\altsyncram_p3c1.tdf (112957, 2006-07-04)
DE2_Default\db\cntr_0i7.tdf (4710, 2006-07-04)
DE2_Default\db\cntr_128.tdf (6913, 2006-07-04)
DE2_Default\db\cntr_5r8.tdf (5430, 2006-07-04)
DE2_Default\db\cntr_728.tdf (9182, 2006-07-04)
DE2_Default\db\cntr_dm8.tdf (6905, 2006-07-04)
DE2_Default\db\cntr_hj7.tdf (15222, 2006-07-04)
DE2_Default\db\cntr_k08.tdf (4702, 2006-07-04)
DE2_Default\db\cntr_lm8.tdf (9928, 2006-07-04)
DE2_Default\db\cntr_m08.tdf (5438, 2006-07-04)
DE2_Default\db\cntr_ol8.tdf (5512, 2006-07-04)
DE2_Default\db\cntr_op7.tdf (10669, 2006-07-04)
DE2_Default\db\cntr_p08.tdf (6542, 2006-07-04)
DE2_Default\db\DE2_Default.(0).cnf.cdb (11067, 2006-07-07)
DE2_Default\db\DE2_Default.(0).cnf.hdb (5770, 2006-07-07)
DE2_Default\db\DE2_Default.(1).cnf.cdb (1576, 2006-07-07)
DE2_Default\db\DE2_Default.(1).cnf.hdb (691, 2006-07-07)
DE2_Default\db\DE2_Default.(10).cnf.cdb (1241, 2006-07-07)
DE2_Default\db\DE2_Default.(10).cnf.hdb (500, 2006-07-07)
DE2_Default\db\DE2_Default.(11).cnf.cdb (21051, 2006-07-07)
DE2_Default\db\DE2_Default.(11).cnf.hdb (1507, 2006-07-07)
DE2_Default\db\DE2_Default.(12).cnf.cdb (12976, 2006-07-07)
DE2_Default\db\DE2_Default.(12).cnf.hdb (6974, 2006-07-07)
DE2_Default\db\DE2_Default.(13).cnf.cdb (81947, 2006-07-07)
DE2_Default\db\DE2_Default.(13).cnf.hdb (30590, 2006-07-07)
DE2_Default\db\DE2_Default.(14).cnf.cdb (12028, 2006-07-07)
DE2_Default\db\DE2_Default.(14).cnf.hdb (4451, 2006-07-07)
DE2_Default\db\DE2_Default.(15).cnf.cdb (7131, 2006-07-07)
DE2_Default\db\DE2_Default.(15).cnf.hdb (1810, 2006-07-07)
DE2_Default\db\DE2_Default.(16).cnf.cdb (8349, 2006-07-07)
DE2_Default\db\DE2_Default.(16).cnf.hdb (1372, 2006-07-07)
DE2_Default\db\DE2_Default.(17).cnf.cdb (13347, 2006-07-07)
DE2_Default\db\DE2_Default.(17).cnf.hdb (4089, 2006-07-07)
DE2_Default\db\DE2_Default.(18).cnf.cdb (8650, 2006-07-07)
DE2_Default\db\DE2_Default.(18).cnf.hdb (1690, 2006-07-07)
... ...
DE2_Default
-----------
This design is the initial design when the board is powered-up. It increments a counter and displays the value on the
7-segment displays and LEDs. An image is also displayed on the VGA port.
Running the Design
------------------
1) Launch the Quartus II software.
2) Open the DE2_Default.qpf project located in the \DE2_Default folder. (File menu -> Open Project)
3) Open the Programmer window. (Tools menu -> Programmer)
4) The DE2_Default.sof programming file should be listed.
Check the 'Program/Configure' box and set up the JTAG programming hardware connection via the 'Hardware Setup' button.
5) Press 'Start' to start programming. The design should now be programmed and running.
User Inputs to the Design
-------------------------
None.
Compiling the Design
--------------------
1) Launch the Quartus II software.
2) Open the DE2_Default.qpf project located in the \DE2_Default folder. (File menu -> Open Project)
3) Start compilation. (Processing -> Start Compilation)
4) After compilation is finished, you can run the design with the generated SOF file. See 'Running the Design' above.
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