文件列表:

altera_avalon_i2c_slave (0, 2006-04-03)
altera_avalon_i2c_slave\cb_generator.pl (31230, 2006-03-27)
altera_avalon_i2c_slave\class.ptf (14886, 2006-03-27)
altera_avalon_i2c_slave\doc (0, 2006-04-06)
altera_avalon_i2c_slave\doc\generic_driver (0, 2006-04-06)
altera_avalon_i2c_slave\doc\generic_driver\altera_avalon_i2c_slave.c (1041, 2006-04-03)
altera_avalon_i2c_slave\doc\generic_driver\altera_avalon_i2c_slave.h (440, 2006-04-03)
altera_avalon_i2c_slave\hdl (0, 2006-04-06)
altera_avalon_i2c_slave\hdl\altera_avalon_i2c_slave.vhd (15817, 2006-04-06)
altera_avalon_i2c_slave\inc (0, 2006-04-03)
altera_avalon_i2c_slave\inc\altera_avalon_i2c_slave_regs.h (1524, 2006-04-03)

-------------------------------------------------- altera_avalon_i2c_slave component -------------------------------------------------- This component is a simple i2c slave receiver. It is designed for simple i2c systems. A sample driver is provided (non - HAL compliant) for simple single transactions. Higher level protocols will have to be implemented by the end user. -------------------------------------------------- Usage: -------------------------------------------------- 1. Address. When calling the init routine the address parameter determines the address this slave will respond to. It is only 7 bits and is automatically left shifted to match the left shifted address during the addres phase of the i2c transaction cycle. It is autotruncated in case the value provided in the init routine is greater than 128. 2. Transmit. Since this is a slave a higher level protocol dictates the timing of transmits (because the master initiates and controls the slave transmit cycle). Regardless when a master does a slave read (slave transmit) the value of the data that is in the data register is transmitted. If no new data is written to the register then the data transmitted is the last data received. This is because the receive and transmit registers are the same register (this could be used as a link status/echo checker for systems that normally only write to the slave). As part of a higher protocol, one could immediately write a value to transmit in this register as part of an ISR that services a receive transaction. Assuming the interrupt latency is much faster than the i2c speed this is an optimal solution. No interrupt is generated for transmits (master read from a slave). Also the ack from a master reading the slave is not checked or verified. 3. Receive. When a master sends data to the slave (and the address matches what was set in the call to init) the component will set the isr bit after receiving the data transmitted. You can poll this bit in the register map or you can enable the interrupt to the cpu and write an ISR to service this interrupt.

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