vxworks-8139(140)1

所属分类:VxWorks
开发工具:C/C++
文件大小:63KB
下载次数:17
上传日期:2007-09-29 23:49:52
上 传 者管理员
说明:  VxWorks下rtl8139网卡驱动 VxWorks下rtl8139网卡驱动
(RTL8139 network card under VxWorks driver RTL8139 NIC driver under VxWorks)

文件列表:
h\drv (0, 2002-07-28)
h\drv\end (0, 2002-07-28)
h\drv\end\unsupported (0, 2002-07-28)
h\drv\end\unsupported\rtl81x9.h (29780, 2001-11-09)
h (0, 2002-07-28)
src\drv (0, 2002-07-28)
src\drv\end (0, 2002-07-28)
src\drv\end\unsupported (0, 2002-07-28)
src\drv\end\unsupported\Makefile (746, 2000-02-07)
src\drv\end\unsupported\rtl81x9.c (102422, 2005-11-24)
src (0, 2002-07-28)
config\pcPentium (0, 2002-07-28)
config\pcPentium\config.h (21615, 2000-02-07)
config\pcPentium\sysLib.c (46476, 2000-02-07)
config\pcPentium\sysRtl81x9End.c (15043, 2000-02-18)
config\pcPentium\configNet.h (4829, 2000-02-09)
config (0, 2002-07-28)

{\rtf1\ansi\ansicpg950\uc2 \deff0\deflang1033\deflangfe1028{\fonttbl{\f0\froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f1\fswiss\fcharset0\fprq2{\*\panose 020b0604020202020204}Arial;} {\f18\froman\fcharset136\fprq2{\*\panose 02020300000000000000}\'b7\'73\'b2\'d3\'a9\'fa\'c5\'e9{\*\falt PMingLiU};}{\f67\froman\fcharset136\fprq2{\*\panose 02020300000000000000}@\'b7\'73\'b2\'d3\'a9\'fa\'c5\'e9;} {\f90\froman\fcharset238\fprq2 Times New Roman CE;}{\f91\froman\fcharset204\fprq2 Times New Roman Cyr;}{\f93\froman\fcharset161\fprq2 Times New Roman Greek;}{\f94\froman\fcharset162\fprq2 Times New Roman Tur;} {\f95\froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\f96\froman\fcharset178\fprq2 Times New Roman (Arabic);}{\f97\froman\fcharset186\fprq2 Times New Roman Baltic;}{\f***\fswiss\fcharset238\fprq2 Arial CE;}{\f99\fswiss\fcharset204\fprq2 Arial Cyr;} {\f101\fswiss\fcharset161\fprq2 Arial Greek;}{\f102\fswiss\fcharset162\fprq2 Arial Tur;}{\f103\fswiss\fcharset177\fprq2 Arial (Hebrew);}{\f104\fswiss\fcharset178\fprq2 Arial (Arabic);}{\f105\fswiss\fcharset186\fprq2 Arial Baltic;} {\f236\froman\fcharset0\fprq2 PMingLiU Western{\*\falt PMingLiU};}{\f628\froman\fcharset0\fprq2 @\'b7\'73\'b2\'d3\'a9\'fa\'c5\'e9 Western;}}{\colortbl;\red0\green0\blue0;\red0\green0\blue255;\red0\green255\blue255;\red0\green255\blue0; \red255\green0\blue255;\red255\green0\blue0;\red255\green255\blue0;\red255\green255\blue255;\red0\green0\blue128;\red0\green128\blue128;\red0\green128\blue0;\red128\green0\blue128;\red128\green0\blue0;\red128\green128\blue0;\red128\green128\blue128; \red192\green192\blue192;}{\stylesheet{\ql \li0\ri0\nowidctlpar\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \fs24\lang1033\langfe1028\kerning2\loch\f0\hich\af0\dbch\af18\cgrid\langnp1033\langfenp1028 \snext0 Normal;}{\*\cs10 \additive Default Paragraph Font;}{\*\cs15 \additive \ul\cf2 \sbasedon10 Hyperlink;}}{\*\listtable{\list\listtemplateid736371140\listhybrid{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext \leveltemplateid-550993538\'02\'00);}{\levelnumbers\'01;}\chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1\fbias1 \fi-360\li360\jclisttab\tx360 }{\listlevel\levelnfc30\levelnfcn30\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0 {\leveltext\leveltemplateid676***713\'02\'01\'a1B;}{\levelnumbers\'01;}\chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li960\jclisttab\tx960 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\levelspace0 \levelindent0{\leveltext\leveltemplateid676***715\'02\'02.;}{\levelnumbers\'01;}\chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li1440\jclisttab\tx1440 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0 \levelindent0{\leveltext\leveltemplateid676***703\'02\'03.;}{\levelnumbers\'01;}\chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li1920\jclisttab\tx1920 }{\listlevel\levelnfc30\levelnfcn30\leveljc0\leveljcn0\levelfollow0\levelstartat1 \levelspace0\levelindent0{\leveltext\leveltemplateid676***713\'02\'04\'a1B;}{\levelnumbers\'01;}\chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li2400\jclisttab\tx2400 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0 \levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid676***715\'02\'05.;}{\levelnumbers\'01;}\chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li2880\jclisttab\tx2880 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0 \levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid676***703\'02\'06.;}{\levelnumbers\'01;}\chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li3360\jclisttab\tx3360 }{\listlevel\levelnfc30\levelnfcn30\leveljc0\leveljcn0 \levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid676***713\'02\'07\'a1B;}{\levelnumbers\'01;}\chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li3840\jclisttab\tx3840 }{\listlevel\levelnfc2\levelnfcn2\leveljc2 \leveljcn2\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid676***715\'02\'08.;}{\levelnumbers\'01;}\chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li4320\jclisttab\tx4320 }{\listname ;}\listid735860165} {\list\listtemplateid1267602954\listhybrid{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid-465799020\'02\'00);}{\levelnumbers\'01;}\chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1\fbias0 \fi-360\li360\jclisttab\tx360 }{\listlevel\levelnfc30\levelnfcn30\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid676***713\'02\'01\'a1B;}{\levelnumbers\'01;}\chbrdr \brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li960\jclisttab\tx960 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid676***715\'02\'02.;}{\levelnumbers\'01;}\chbrdr \brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li1440\jclisttab\tx1440 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid676***703\'02\'03.;}{\levelnumbers\'01;}\chbrdr \brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li1920\jclisttab\tx1920 }{\listlevel\levelnfc30\levelnfcn30\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid676***713\'02\'04\'a1B;}{\levelnumbers\'01;} \chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li2400\jclisttab\tx2400 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid676***715\'02\'05.;}{\levelnumbers\'01;} \chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li2880\jclisttab\tx2880 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid676***703\'02\'06.;}{\levelnumbers\'01;} \chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li3360\jclisttab\tx3360 }{\listlevel\levelnfc30\levelnfcn30\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid676***713\'02\'07\'a1B;}{\levelnumbers \'01;}\chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li3840\jclisttab\tx3840 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\leveltemplateid676***715\'02\'08.;}{\levelnumbers \'01;}\chbrdr\brdrnone\brdrcf1 \chshdng0\chcfpat1\chcbpat1 \fi-480\li4320\jclisttab\tx4320 }{\listname ;}\listid2133133010}}{\*\listoverridetable{\listoverride\listid2133133010\listoverridecount0\ls1}{\listoverride\listid735860165\listoverridecount0\ls2}} {\info{\author victor}{\operator victorh}{\creatim\yr2002\mo7\dy28\hr10\min14}{\revtim\yr2005\mo11\dy24\hr18\min39}{\version4}{\edmins3}{\nofpages4}{\nofwords728}{\nofchars4151}{\*\company \'a4\'bd\'a5\'71\'a6\'57\'ba\'d9\'a5\'bc\'aa\'be}{\nofcharsws0} {\vern8269}}\paperw12240\paperh15840\margl1800\margr1800\margt1440\margb1440\gutter0 \ftnbj\aenddoc\hyphcaps0\horzdoc\dghspace120\dgvspace120\dghorigin1701\dgvorigin1***4\dghshow0\dgvshow3\jcompress\viewkind4\viewscale100 \fet0\sectd \linex0\sectdefaultcl {\*\pnseclvl1\pnucrm\pnstart1\pnindent720\pnhang{\pntxta \dbch .}}{\*\pnseclvl2\pnucltr\pnstart1\pnindent720\pnhang{\pntxta \dbch .}}{\*\pnseclvl3\pndec\pnstart1\pnindent720\pnhang{\pntxta \dbch .}}{\*\pnseclvl4\pnlcltr\pnstart1\pnindent720\pnhang {\pntxta \dbch )}}{\*\pnseclvl5\pndec\pnstart1\pnindent720\pnhang{\pntxtb \dbch (}{\pntxta \dbch )}}{\*\pnseclvl6\pnlcltr\pnstart1\pnindent720\pnhang{\pntxtb \dbch (}{\pntxta \dbch )}}{\*\pnseclvl7\pnlcrm\pnstart1\pnindent720\pnhang{\pntxtb \dbch (} {\pntxta \dbch )}}{\*\pnseclvl8\pnlcltr\pnstart1\pnindent720\pnhang{\pntxtb \dbch (}{\pntxta \dbch )}}{\*\pnseclvl9\pnlcrm\pnstart1\pnindent720\pnhang{\pntxtb \dbch (}{\pntxta \dbch )}}\pard\plain \ql \li0\ri0\nowidctlpar\faauto\rin0\lin0\itap0 \fs24\lang1033\langfe1028\kerning2\loch\af0\hich\af0\dbch\af18\cgrid\langnp1033\langfenp1028 {\fs20\lang1028\langfe1028\kerning0\loch\af18\langnp1028 \par }{\fs20\kerning0\loch\af18 \hich\af0\dbch\af18\loch\f18 README: RTL81x9 END Driver \par \par \hich\af0\dbch\af18\loch\f18 This file contains information regarding the RTL81x9 End Driver. \par \hich\af0\dbch\af18\loch\f18 \par }\pard \ql \li0\ri0\nowidctlpar\brdrb\brdrs\brdrw15\brsp20 \faauto\rin0\lin0\itap0 {\fs20\kerning0\loch\af18 \par }\pard \ql \li0\ri0\nowidctlpar\faauto\rin0\lin0\itap0 {\fs20\kerning0\loch\af18 \hich\af0\dbch\af18\loch\f18 RELEASE 1.}{\fs20\kerning0\loch\af18 \hich\af0\dbch\af18\loch\f18 4 \par {\listtext\pard\plain\fs20 \hich\af0\dbch\af18\loch\f18 1)\tab}}\pard \ql \fi-360\li360\ri0\nowidctlpar\jclisttab\tx360\faauto\ls2\rin0\lin360\itap0 {\fs20\kerning0\loch\af18 \hich\af0\dbch\af18\loch\f18 Wait DMA complete to send packet. \par }\pard \ql \li0\ri0\nowidctlpar\faauto\rin0\lin0\itap0 {\field{\*\fldinst {\fs20\kerning0\loch\af18 \hich\af0\dbch\af18\loch\f18 \hich\af0\dbch\af18\loch\f18 HYPERLINK \hich\af0\dbch\af18\loch\f18 "\hich\af0\dbch\af18\loch\f18 mailto:}{ \fs20\kerning0\loch\af18 \hich\af0\dbch\af18\loch\f18 victorh@realtek.com.tw}{\fs20\kerning0\loch\af18 \hich\af0\dbch\af18\loch\f18 "\hich\af0\dbch\af18\loch\f18 }{\fs20\kerning0\loch\af18 {\*\datafield 00d0c9ea79f9bace118c8200aa004ba90b02000000170000001700000076006900630074006f007200680040007200650061006c00740065006b002e0063006f006d002e00740077000000e0c9ea79f9bace118c8200aa004ba90b3c0000006d00610069006c0074006f003a0076006900630074006f007200680040007200 650061006c00740065006b002e0063006f006d002e00740077000000}}}{\fldrslt {\cs15\fs20\ul\cf2\kerning0\loch\af18 \hich\af0\dbch\af18\loch\f18 victorh@realtek.com.tw}}}{\fs20\kerning0\loch\af18 \hich\af0\dbch\af18\loch\f18 \hich\af0\dbch\af18\loch\f18 2005.11.24 \par }{\fs20\kerning0\loch\af18 \hich\af0\dbch\af18\loch\f18 RELEASE 1.}{\f1\fs20\kerning0 \hich\af1\dbch\af18\loch\f1 2 \par {\listtext\pard\plain\f1\fs20 \hich\af1\dbch\af18\loch\f1 1)\tab}}\pard \ql \fi-360\li360\ri0\nowidctlpar\jclisttab\tx360\faauto\ls1\rin0\lin360\itap0 {\f1\fs20\kerning0 \hich\af1\dbch\af18\loch\f1 Remove NETCLFREE when tx abort in }{ \hich\af0\dbch\af18\loch\f0 rtl81x9HandleTxInt}{\f1\fs20\kerning0 \hich\af1\dbch\af18\loch\f1 . \par }\pard \ql \li0\ri0\nowidctlpar\faauto\rin0\lin0\itap0 {\f1\fs20\kerning0 \hich\af1\dbch\af18\loch\f1 victorh@realtek.com.tw \par }{\fs20\kerning0\loch\af18 \par \hich\af0\dbch\af18\loch\f18 RELEASE 1.}{\f1\fs20\kerning0 \hich\af1\dbch\af18\loch\f1 1 \par }{\f18\fs20\kerning0 \hich\af1\dbch\af18\loch\f18 There changes are as follows: \par }{\f1\fs20\kerning0 \hich\af1\dbch\af18\loch\f1 1) The previous driver can not support poll mode. \par \hich\af1\dbch\af18\loch\f1 2) Fix the ping() test packet size cant not large than 6000 bytes. \par \hich\af1\dbch\af18\loch\f1 3) Fix the GPF(genernal protect fault) bug. When down load a 6M bytes im\hich\af1\dbch\af18\loch\f1 age file the debug mode will issue a GPF. \par \hich\af1\dbch\af18\loch\f1 4) support 8100/8101/8102 , no problem. \par \par \hich\af1\dbch\af18\loch\f1 victorh@realtek.com.tw}{\fs20\kerning0\loch\af18 \par \par \par }{\f18\fs20\kerning0 \hich\af1\dbch\af18\loch\f18 RELEASE 1.0/EA}{\f1\fs20\kerning0 \hich\af1\dbch\af18\loch\f1 4 \par \hich\af1\dbch\af18\loch\f1 From now on Realtek maintain the 8139X series of Vxworks driver. \par }{\f18\fs20\kerning0 \hich\af1\dbch\af18\loch\f18 There changes are as follows: \par }{\f1\fs20\kerning0 \par \hich\af1\dbch\af18\loch\f1 1) Change the MAXDMABURST size to \hich\af1\dbch\af18\loch\f1 1024 on RX and TX. \par \hich\af1\dbch\af18\loch\f1 2) FIX the buffer overflow bug. When buffer overflow the receive path stop to forward packet . \par }{\fs20\kerning0\loch\af18 \par \par }{\f18\fs20\kerning0 \hich\af1\dbch\af18\loch\f18 Please send comments and problems to \par \par \par }{\f1\fs20\kerning0 \hich\af1\dbch\af18\loch\f1 victorh@realtek.com.tw}{\fs20\kerning0\loch\af18 \par \par \par \par }{\f18\fs20\kerning0 \hich\af1\dbch\af18\loch\f18 RELEASE 1.0/EA3 \par \par \hich\af1\dbch\af18\loch\f18 This third early access release incorporates some of the feedback from \par \hich\af1\dbch\af18\loch\f18 beta testing in the field and some of the problems found in subsequent \par \hich\af1\dbch\af18\loch\f18 in house testing. \par \par \hich\af1\dbch\af18\loch\f18 There changes are as follows: \par \par \hich\af1\dbch\af18\loch\f18 1) sysRtl81x9.c has been modified to mask the reserved and unuse\hich\af1\dbch\af18\loch\f18 d interrupt \par \hich\af1\dbch\af18\loch\f18 bits, when checking the status of the incoming interrupt. \par \par \hich\af1\dbch\af18\loch\f18 2) rtl81x9HandleRecvInt.c moved more of the message processing within \par \hich\af1\dbch\af18\loch\f18 the loop that checks whether the Rx Buffer is empty. \par \par \hich\af1\dbch\af18\loch\f18 3) rtl81x9Wait.c has been altered to correct the problem whe\hich\af1\dbch\af18\loch\f18 reby the \par \hich\af1\dbch\af18\loch\f18 timeout was always reported due to incorrect logic. \par \par \hich\af1\dbch\af18\loch\f18 RELEASE 1.0/EA2 \par \par \hich\af1\dbch\af18\loch\f18 This second early access release incorporates some of the feedback from \par \hich\af1\dbch\af18\loch\f18 beta testing in the field and some of the problems found in subsequent \par \hich\af1\dbch\af18\loch\f18 in house testing. \par \par \hich\af1\dbch\af18\loch\f18 There are three key area that have been changed over EA1 release and they \par \hich\af1\dbch\af18\loch\f18 are as follows: \par \par \hich\af1\dbch\af18\loch\f18 1) sysRtl81x9.c has been modified to allow multiple rtl cards to work within \par \hich\af1\dbch\af18\loch\f18 one target. \par \par \hich\af1\dbch\af18\loch\f18 Note: for multiple units, configNet.h has to altered to add a second endloa\hich\af1\dbch\af18\loch\f18 d \par \hich\af1\dbch\af18\loch\f18 line with 2 as the first parameter for unit. \par \par \hich\af1\dbch\af18\loch\f18 2) sysRtl81x9.c has been modified to allow the user to set the Early \par \hich\af1\dbch\af18\loch\f18 Rx Threshold value. This value dictates the percentage of the Received message \par \hich\af1\dbch\af18\loch\f18 that should be read into the FIFO before starting to move \hich\af1\dbch\af18\loch\f18 the message over to \par \hich\af1\dbch\af18\loch\f18 the receive buffer. It works on fractions of sixteenths. This value can be \par \hich\af1\dbch\af18\loch\f18 altered via the define RTL81X9_EARX_THRESH. It has been found that the best \par \hich\af1\dbch\af18\loch\f18 value for this register depends largely on the users individual card and \par \hich\af1\dbch\af18\loch\f18 performa\hich\af1\dbch\af18\loch\f18 nce of target, therefore by placing it here the driver does not need to \par \hich\af1\dbch\af18\loch\f18 be altered and recompiled. The value has been set to 10 by default, but can be \par \hich\af1\dbch\af18\loch\f18 changed to improve the performance of the driver. \par \par \hich\af1\dbch\af18\loch\f18 This change also effects rtl81x9.c and rtl81x9.h \par \par \hich\af1\dbch\af18\loch\f18 3) \hich\af1\dbch\af18\loch\f18 rtl81x9.c has been aletered to correct a mistake found in the \par \hich\af1\dbch\af18\loch\f18 rtl81x9CsrReadByte function. \par \par \hich\af1\dbch\af18\loch\f18 RELEASE 1.0/EA1 \par \tab \par \tab \hich\af1\dbch\af18\loch\f18 First release for Tornado 2.0 \par \par \hich\af1\dbch\af18\loch\f18 This is the first draft release of the RTL81x9 END Driver. It has to this date \par \hich\af1\dbch\af18\loch\f18 only been tested with Tornado 2.0, and the files provided here are for direct \par \hich\af1\dbch\af18\loch\f18 inclusion within Tornado 2.0. \par \par \hich\af1\dbch\af18\loch\f18 It is intended that the Tar file provided with this download should only \par \hich\af1\dbch\af18\loch\f18 be used internally to Wind River Systems. The Tar file should be untarred \hich\af1\dbch\af18\loch\f18 using \par \hich\af1\dbch\af18\loch\f18 the tar -xvf command from the windbase directory. \par \par \hich\af1\dbch\af18\loch\f18 Contained within this tar the following files will be found: \par \par \hich\af1\dbch\af18\loch\f18 target/config/pcPentium: \par \par \hich\af1\dbch\af18\loch\f18 config.h \par \hich\af1\dbch\af18\loch\f18 configNet.h \par \hich\af1\dbch\af18\loch\f18 sysRtl81x9.c \par \hich\af1\dbch\af18\loch\f18 sysLib.c \par \par \hich\af1\dbch\af18\loch\f18 NOTE: Copies of existing files should be made prior to the untarri\hich\af1\dbch\af18\loch\f18 ng of this \par \hich\af1\dbch\af18\loch\f18 drivers files. \par \par \hich\af1\dbch\af18\loch\f18 target\\h\\drv\\end\\unsupported: \par \par \hich\af1\dbch\af18\loch\f18 rtl81x9.h \par \par \hich\af1\dbch\af18\loch\f18 target\\src\\drv\\end\\unsupported: \par \par \hich\af1\dbch\af18\loch\f18 rtl81x9.c \par \hich\af1\dbch\af18\loch\f18 Makefile \par \par \par \hich\af1\dbch\af18\loch\f18 Once the files have been installed into the Tornado 2.0 tree, the driver should \par \hich\af1\dbch\af18\loch\f18 be built using the make CPU=PENTIUM command from within the \par \hich\af1\dbch\af18\loch\f18 target\\src\\drv\\end\\unsupported directory. \par \par \hich\af1\dbch\af18\loch\f18 Then the vxWorks image and bootrom should be built in the normal manner. \par \par \hich\af1\dbch\af18\loch\f18 The interface name for the driver is 'rtl'. \par \par \par \par \par \hich\af1\dbch\af18\loch\f18 Additional Notes \par \hich\af1\dbch\af18\loch\f18 -------------\hich\af1\dbch\af18\loch\f18 --- \par \par \par \hich\af1\dbch\af18\loch\f18 This driver has been tested using a rtl8139A and a rtl8139B board, although it \par \hich\af1\dbch\af18\loch\f18 is intended and believed that this driver should work for the rtl8129 series \par \hich\af1\dbch\af18\loch\f18 of boards as well. \par \par \hich\af1\dbch\af18\loch\f18 Within the rtl81x9.h file, different manufacturers device id's are stored\hich\af1\dbch\af18\loch\f18 , \par \hich\af1\dbch\af18\loch\f18 if there are problems with initialisation of your board then it is possible \par \hich\af1\dbch\af18\loch\f18 that these will need to be updated to include your board. \par \par \hich\af1\dbch\af18\loch\f18 The driver has had minimal testing, and therefore all feedback on problems \par \hich\af1\dbch\af18\loch\f18 encountered will be appreciated. \par \par \hich\af1\dbch\af18\loch\f18 The only \hich\af1\dbch\af18\loch\f18 known problem is that during the initialisation, a muxLoad fail is \par \hich\af1\dbch\af18\loch\f18 reported even though the system correctly initialises and boots. It is \par \hich\af1\dbch\af18\loch\f18 believed that this is due to a problem with the identification of the boards \par \hich\af1\dbch\af18\loch\f18 in the target, and the attempted initialisation of a no-existant board as \par \hich\af1\dbch\af18\loch\f18 well as the valid board. \par \par \hich\af1\dbch\af18\loch\f18 The driver by default, if available attempts to go into auto-negotiation \par \hich\af1\dbch\af18\loch\f18 during initialisation, this has necessitated a large delay to be placed in \par \hich\af1\dbch\af18\loch\f18 the ini\hich\af1\dbch\af18\loch\f18 tialisation routine. \par \par \hich\af1\dbch\af18\loch\f18 Feedback from Sales giving pricing guidelines for this driver would be useful. \par \par \par \par \par \par \hich\af1\dbch\af18\loch ... ...

近期下载者

相关文件


收藏者