Afixed-pointbasecomplementdivider

所属分类:VHDL/FPGA/Verilog
开发工具:Others
文件大小:140KB
下载次数:9
上传日期:2007-10-02 20:06:08
上 传 者lanshewuyu
说明:   由寄存器,全加器,移位寄存器,计数器,触发器和门电路构成补码一位除法器,将开关设定的补码形式出现的除数,被除数存入相应寄存器中.能用单脉冲按步演示运算全过程.
(From the register, full adder, shift register, counters, flip-flops and gates constitute a complement divider will switch set in the form of complement divisor, dividend deposited in the corresponding register. Monopulse can be used by step-by-step demonstration of the entire process of computing.)

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Afixed-pointbasecomplementdivider.rar.doc (188928, 2007-08-06)

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