文件列表:

arith_lib-1.0\doc (0, 1998-02-04)
arith_lib-1.0\arith_lib_standard.zip (81967, 1998-05-28)
arith_lib-1.0\arith_lib_cadence.zip (82394, 1998-05-28)
arith_lib-1.0\arith_lib_synopsys.zip (81139, 1998-05-28)
arith_lib-1.0 (0, 2003-05-05)

VHDL Library of Arithmetic Units, Version 1.0 ============================================= Installation: 1) Unpack the appropriate tar file (standard, cadence, or synopsys) -> generates a directory `vhdl' containing all VHDL files. 2) Create a new `arith_lib' library in your synthesis environment (see instructions of your synthesis tool). 3) Compile the required VHDL files into this library: - first the `arith_utils.vhd' and `arith_lib.vhd' files - then the required component files (see the `hierarchy.txt' file for component dependencies). Usage: - The components can be used by simple instantiation in your VHDL code - All component declarations are found in the `arith_lib' package - See the `Example.vhd' file for usage example - Select the performance of the component through the `speed' generic: slow, medium, fast (0, 1, 2 under Synopsys) - Make sure that your synthesizer takes full-adder cells if synthesizing `FullAdder.vhd' (many arithmetic units have much better performance using full-adders). If necessary, instantiate the according full-adder cell directly in `FullAdder.vhd'. - The components are highly hierarchical. Flatten the synthesized circuits before optimization in order to get better optimization results. - Multipliers and multi-operand adders contain redundant full-adders. In some tools, the netlist must be optimized several times in order to eliminate all redundant full-adders. Documentation: - A list of all components is given in `components.txt'. - Hierarchical dependencies of the components are given in `hierarchy.txt'. - Component declarations are found in `arith_lib.vhd'. - Detailed component information and behavioral descriptions are given in the individual VHDL source files. - A technical report on the library and a project description is found at . - This library and Documentation also can be downloaded from http://www.fpga.com.cn Maintenance: - This library was exhaustively tested only on V-System and Compass. It was marginally tested on Mentor, Cadence, and Synopsys. I am very interested in feedback on these and other tools with respect to problems during simulation or synthesis as well as circuit performance. - Please send reports to .

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