testbench
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：30KB
下载次数：88
上传日期：2007-10-10 16:25:40
上 传 者：
nandgate
说明： 一个自己编写的全数字锁相环及其测试向量，比较简单但功能基本达到。
(I have written an all-digital phase-locked loop and its test vectors, relatively simple to achieve but the basic function.)
文件列表:
testbench\ADPLL.cr.mti (2, 2006-09-21)
testbench\adpll.mpf (20587, 2007-05-22)
testbench\ADPLL.v (1569, 2006-09-21)
testbench\ADPLL.v.bak (1569, 2006-09-21)
testbench\tb_adpll.acf (14839, 2007-07-09)
testbench\tb_adpll.hif (1520, 2007-07-09)
testbench\tb_ADPLL.v (2080, 2006-09-21)
testbench\tb_ADPLL.v.bak (2080, 2006-09-21)
testbench\vsim.wlf (32768, 2006-09-21)
testbench\work\@a@d@p@l@l\verilog.asm (17085, 2007-05-22)
testbench\work\@a@d@p@l@l\_primary.dat (967, 2007-05-22)
testbench\work\@a@d@p@l@l\_primary.vhd (489, 2007-05-22)
testbench\work\@a@d@p@l@l (0, 2007-05-29)
testbench\work\tb_@a@d@p@l@l\verilog.asm (17751, 2007-05-22)
testbench\work\tb_@a@d@p@l@l\_primary.dat (1416, 2007-05-22)
testbench\work\tb_@a@d@p@l@l\_primary.vhd (217, 2007-05-22)
testbench\work\tb_@a@d@p@l@l (0, 2007-05-29)
testbench\work\_info (577, 2007-05-22)
testbench\work (0, 2007-05-29)
testbench (0, 2007-07-09)
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