文件列表:

rs32_28_8 (0, 1998-10-01)
rs32_28_8\chien.vhd (8128, 1998-10-01)
rs32_28_8\COPYRIGHT (995, 1998-06-02)
rs32_28_8\euclid.vhd (14278, 1998-10-01)
rs32_28_8\gfmul.vhd (780, 1998-10-01)
rs32_28_8\gfnorm.vhd (3761, 1998-10-01)
rs32_28_8\make_script (245, 1998-10-01)
rs32_28_8\omcalc.vhd (7762, 1998-10-01)
rs32_28_8\rsdec_tb.vhd (6795, 1998-10-01)
rs32_28_8\rsdec_top.vhd (9766, 1998-10-01)
rs32_28_8\rs_pkg.vhd (12755, 1998-10-01)
rs32_28_8\sram_premul.vhd (1302, 1998-10-01)
rs32_28_8\sram_sigma.vhd (1433, 1998-10-01)
rs32_28_8\sram_synd.vhd (1426, 1998-10-01)
rs32_28_8\sram_word.vhd (1432, 1998-10-01)
rs32_28_8\syndcalc.vhd (2492, 1998-10-01)
rs32_28_8\wordmem.vhd (3248, 1998-10-01)

############################################################################## README for the 'rs32_28_8' package Author: Christian Schuler GMD-FOKUS Research Institute for Open Communication Systems Berlin, Germany email : schuler@fokus.gmd.de homepage: http://www.fokus.gmd.de/usr/schuler Version: V 1.1, 1.10.*** ############################################################################## Description: The package contains Reed-Solomon (RS) FEC decoder in VHDL. The code has been generated by the code generator 'genrs'. The package contains - synthesizable VHDL code (RTL level) for a RS(32,28) decoder - VHDL testbench for simulation - use of on chip RAM components Caution: The RS decoder is probably not the optimum solution for every application, and there are many points, where the VHDL code might be further optimized the improve delay or area of the design ! The code has been tested with Model Technology Simulator V5.1c, the Exemplar Logic Leonardo V4.2 synthesis tool and XILINX XC4000EX FPGA's as target technology. The VHDL model consists of 14 files: chien.vhd omcalc.vhd sram_premul.vhd syndcalc.vhd euclid.vhd rs_pkg.vhd sram_sigma.vhd wordmem.vhd gfmul.vhd rsdec_tb.vhd sram_synd.vhd gfnorm.vhd rsdec_top.vhd sram_word.vhd The 'make_script' can be used to compile all files for simulation, but it has to be adapted to the simulation environment. For synthesis all files except the testbench ('rsdec_tb.vhd') have to be read in the right order, which can be taken form the 'make_script'. ############################################################################## Acknowledgements: Author : Christian Schuler Research Institute for Open Communication Systems GMD FOKUS, Kaiserin-Augusta-Allee 31, D-10589 Berlin, Germany Phone : ++49 / (0)30 / 34 63 - 7295 Fax : ++49 / (0)30 / 34 63 - 8295 Email : schuler@fokus.gmd.de Homepage : http://www.fokus.gmd.de/usr/schuler ############################################################################## Restrictions: THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. ############################################################################## Limitations / Know Errors: The component sram_premul.vhd contains actually a ROM, which must be initialized during configuration for XILINX technologies !

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