说明：   DPLL由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍) 为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低.
(DPLL phase detector by the addition and subtraction counter modulus K synchronous pulse addition and subtraction circuit detection circuit establishing mode N divider constituted. The entire system of the center frequency (ie signal_in and signal_out the code rate of 2 times) for clk/8/N. Modulus K addition and subtraction of the K value of Counter DPLL decision accuracy and synchronization set-up time, K the greater the synchronization set-up time is long, synchronous and high accuracy. In contrast the short and low.)