2
所属分类：VHDL/FPGA/Verilog
开发工具：Flex
文件大小：192KB
下载次数：1
上传日期：2007-11-02 06:49:20
上 传 者：
pxh86
说明： 8位计数器，可逆，可加可减，可以以时钟输入也可手动输入
(8-bit counter, reversible, can be increased or decreased, can be input clock can also manually enter)
文件列表:
2 (0, 2007-11-02)
2\cmp_state.ini (3, 2007-11-01)
2\counter.asm.rpt (8779, 2007-11-01)
2\counter.cdf (335, 2007-11-01)
2\counter.done (26, 2007-11-01)
2\counter.fit.eqn (14209, 2007-11-01)
2\counter.fit.rpt (31635, 2007-11-01)
2\counter.flow.rpt (3813, 2007-11-01)
2\counter.map.eqn (12343, 2007-11-01)
2\counter.map.rpt (16955, 2007-11-01)
2\counter.pin (12237, 2007-11-01)
2\counter.pof (212108, 2007-11-01)
2\counter.qpf (1569, 2007-11-01)
2\counter.qsf (2983, 2007-11-01)
2\counter.qws (2331, 2007-11-01)
2\counter.sim.rpt (5094, 2007-11-01)
2\counter.sof (14454, 2007-11-01)
2\counter.tan.rpt (38356, 2007-11-01)
2\counter.tan.summary (946, 2007-11-01)
2\counter.vhd (667, 2007-11-01)
2\counter.vwf (9443, 2007-11-01)
2\db (0, 2007-11-02)
2\db\add_sub_12h.tdf (3752, 2007-11-01)
2\db\add_sub_rch.tdf (3885, 2007-11-01)
2\db\counter(0).cnf.cdb (3628, 2007-11-01)
2\db\counter(0).cnf.hdb (1011, 2007-11-01)
2\db\counter(1).cnf.cdb (1195, 2007-11-01)
2\db\counter(1).cnf.hdb (524, 2007-11-01)
2\db\counter(10).cnf.cdb (1616, 2007-11-01)
2\db\counter(10).cnf.hdb (683, 2007-11-01)
2\db\counter(11).cnf.cdb (1476, 2007-11-01)
2\db\counter(11).cnf.hdb (557, 2007-11-01)
2\db\counter(12).cnf.cdb (3505, 2007-11-01)
2\db\counter(12).cnf.hdb (675, 2007-11-01)
2\db\counter(13).cnf.cdb (1197, 2007-11-01)
2\db\counter(13).cnf.hdb (528, 2007-11-01)
2\db\counter(14).cnf.cdb (1866, 2007-11-01)
2\db\counter(14).cnf.hdb (709, 2007-11-01)
2\db\counter(2).cnf.cdb (1866, 2007-11-01)
2\db\counter(2).cnf.hdb (688, 2007-11-01)
... ...
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