xillybus-eval-kintex7-2.0c

所属分类嵌入式/单片机/硬件编程
开发工具:VHDL
文件大小:539KB
下载次数:0
上传日期:2018-06-14 11:34:56
上 传 者zcr214
说明:  xillybus示例程序,已修改适用kc705
(Xillybus sample program that has been modified for kc705)

文件列表
xillybus-eval-kintex7-2.0c, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\README.TXT, 3144 , 2017-11-12
xillybus-eval-kintex7-2.0c\core, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\core\xillybus_core.ngc, 2030898 , 2017-11-12
xillybus-eval-kintex7-2.0c\instantiation templates, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\instantiation templates\template.v, 3473 , 2017-11-12
xillybus-eval-kintex7-2.0c\instantiation templates\template.vhd, 6036 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\src, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\src\xillybus_core.v, 1797 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\src\xillybus_block.v, 16201 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\xgui, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\xgui\xpgui.tcl, 181 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\xci, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\xci\fifo_xillybus_8, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\xci\fifo_xillybus_8\fifo_xillybus_8.xci, 52048 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\xci\fifo_xillybus_fwft_8, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\xci\fifo_xillybus_fwft_8\fifo_xillybus_fwft_8.xci, 52068 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\xci\fifo_xillybus_32, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\xci\fifo_xillybus_32\fifo_xillybus_32.xci, 52040 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\xci\fifo_xillybus_fwft_32, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\xci\fifo_xillybus_fwft_32\fifo_xillybus_fwft_32.xci, 52060 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillybus_block\component.xml, 33118 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\blockdesign, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\blockdesign\blockdesign.bd, 7510 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\src, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\src\xillydemo.v, 553 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\src\detach_clocks.xdc, 376 , 2017-11-12
xillybus-eval-kintex7-2.0c\blockdesign\xillydemo-vivado.tcl, 4742 , 2017-11-12
xillybus-eval-kintex7-2.0c\vivado-essentials, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\vivado-essentials\pcie_k7_vivado, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\vivado-essentials\pcie_k7_vivado\pcie_k7_vivado.xci, 61922 , 2017-11-12
xillybus-eval-kintex7-2.0c\vivado-essentials\pcie_k7_8x_pipe_clock.v, 2064 , 2017-11-12
xillybus-eval-kintex7-2.0c\vivado-essentials\showstopper.tcl, 1602 , 2017-11-12
xillybus-eval-kintex7-2.0c\vivado-essentials\fifo_32x512, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\vivado-essentials\fifo_32x512\fifo_32x512.xci, 51964 , 2017-11-12
xillybus-eval-kintex7-2.0c\vivado-essentials\xillydemo.xdc, 1036 , 2017-11-12
xillybus-eval-kintex7-2.0c\vivado-essentials\fifo_8x2048, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\vivado-essentials\fifo_8x2048\fifo_8x2048.xci, 51992 , 2017-11-12
xillybus-eval-kintex7-2.0c\vivado-essentials\pcie_k7_8x.v, 13850 , 2017-11-12
xillybus-eval-kintex7-2.0c\verilog, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\verilog\xillydemo.xise, 47483 , 2017-11-12
xillybus-eval-kintex7-2.0c\verilog\src, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\verilog\src\xillybus_kc705.ucf, 4350 , 2017-11-12
xillybus-eval-kintex7-2.0c\verilog\src\xillybus.v, 11590 , 2017-11-12
xillybus-eval-kintex7-2.0c\verilog\src\fifo_32x512.xco, 7090 , 2017-11-12
xillybus-eval-kintex7-2.0c\verilog\src\xillydemo.v, 4868 , 2017-11-12
xillybus-eval-kintex7-2.0c\verilog\src\fifo_8x2048.xco, 7113 , 2017-11-12
xillybus-eval-kintex7-2.0c\verilog\src\xillybus_core.v, 1797 , 2017-11-12
xillybus-eval-kintex7-2.0c\verilog\xillydemo-vivado.tcl, 3717 , 2017-11-12
xillybus-eval-kintex7-2.0c\pcie_core, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\pcie_core\pcie_core.xise, 37504 , 2017-11-12
xillybus-eval-kintex7-2.0c\pcie_core\pcie_k7_8x.xco, 7476 , 2017-11-12
xillybus-eval-kintex7-2.0c\vhdl, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\vhdl\xillydemo.xise, 47507 , 2017-11-12
xillybus-eval-kintex7-2.0c\vhdl\src, 0 , 2017-11-12
xillybus-eval-kintex7-2.0c\vhdl\src\xillybus_kc705.ucf, 4350 , 2017-11-12
xillybus-eval-kintex7-2.0c\vhdl\src\xillybus.v, 11590 , 2017-11-12
xillybus-eval-kintex7-2.0c\vhdl\src\fifo_32x512.xco, 7090 , 2017-11-12
xillybus-eval-kintex7-2.0c\vhdl\src\fifo_8x2048.xco, 7113 , 2017-11-12
xillybus-eval-kintex7-2.0c\vhdl\src\xillybus_core.v, 1797 , 2017-11-12
xillybus-eval-kintex7-2.0c\vhdl\src\xillydemo.vhd, 8498 , 2017-11-12
xillybus-eval-kintex7-2.0c\vhdl\xillydemo-vivado.tcl, 3716 , 2017-11-12

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