xapp861
所属分类：单片机开发
开发工具：Visual C++
文件大小：57KB
下载次数：26
上传日期：2007-11-26 19:06:37
上 传 者：
DAOZI
说明： 使用ＩＤＥＬＡＹ实现８倍过采样异步串行信号恢复信号
(IDELAY use to achieve 8 times oversampling asynchronous serial signal to restore the signal)
文件列表:
xapp861r10 (0, 2006-09-22)
xapp861r10\manifest.txt (1192, 2006-09-22)
xapp861r10\Verilog (0, 2006-09-22)
xapp861r10\Verilog\example_sdsdi_lvds_top.ucf (3917, 2006-09-22)
xapp861r10\Verilog\example_sdsdi_lvds_top.v (10320, 2006-09-22)
xapp861r10\Verilog\oversample_8x.v (12721, 2006-09-22)
xapp861r10\Verilog\par_descrambler.v (5952, 2004-10-15)
xapp861r10\Verilog\par_framer.v (19683, 2005-01-18)
xapp861r10\VHDL (0, 2006-09-22)
xapp861r10\VHDL\example_sdsdi_lvds_top.ucf (3917, 2006-09-22)
xapp861r10\VHDL\example_sdsdi_lvds_top.vhd (15155, 2006-09-22)
xapp861r10\VHDL\ff_fifo2e.vhd (4216, 2006-09-22)
xapp861r10\VHDL\ff_fifo2e_10b.vhd (4482, 2006-09-22)
xapp861r10\VHDL\os48_1011x20bTo10b.vhd (13850, 2006-09-22)
xapp861r10\VHDL\os48_1011x20bTo10b_top2.vhd (12947, 2006-09-22)
xapp861r10\VHDL\osDeci20b_48_1011x_BRAM.vhd (11106, 2006-09-22)
xapp861r10\VHDL\oversample_8x.vhd (18146, 2006-09-22)
xapp861r10\VHDL\par_descrambler.vhd (6669, 2004-08-27)
xapp861r10\VHDL\par_framer.vhd (27195, 2004-08-27)
xapp861r10\VHDL\PKG_OVERSAMP.vhd (11179, 2006-09-22)
xapp861r10\VHDL\PKG_XILINX.vhd (32012, 2006-09-22)
xapp861r10\VHDL\sipoCtl10b_BRAM_v2.vhd (11935, 2006-09-22)
xapp861r10\VHDL\sipoCtl10b_BRAM_v2_virtex5.vhd (12631, 2006-09-22)
XAPP861 version 1.0 reference design files:
Verilog Directory:
example_sdsdi_lvds_top.v Top level example reference desing
example_sdsdi_lvds_top.ucf Constraint file for top level example
oversample_8x.v 8X oversampler module
par_descrambler.v SMPTE 259M SD-SDI descrambler
par_framer.v SMPTE 259M SD-SDI framer
VHDL Directory:
example_sdsdi_lvds_top.vhd Top level example reference desing
example_sdsdi_lvds_top.ucf Constraint file for top level example
oversample_8x.vhd 8X oversampler module
par_descrambler.vhd SMPTE 259M SD-SDI descrambler
par_framer.vhd SMPTE 259M SD-SDI framer
ff_fifo2e.vhd DRU file
ff_fifo2e_10b.vhd DRU file
os48_1011x20bTo10b.vhd DRU file
os48_1011x20bTo10b_top2.vhd Top level of DRU
osDeci20b_48_1011x_BRAM.vhd DRU file
sipoCtl10b_BRAM_v2.vhd DRU SIPO control for Virtex-4
sipoCtl10b_BRAM_v2_virtex5.vhd DRU SIPO control for Virtex-5
PKG_OVERSAMP.vhd Package file for DRU
PKG_XILINX.vhd Package file for DRU
Revision History
----------------
Release 1.0: 2006/09/22:
Initial release of IDELAY-based 8X oversampler.
The oversample_8x module and the top level example files are available in
both Verilog and VHDL. However, the DRU is only available in VHDL. Use mixed
language simulation and synthesis to include this DRU in a Verilog design.
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