文件列表:

rtl_release (0, 2006-05-08)
rtl_release\par (0, 2006-05-08)
rtl_release\par\mem_tb_top.ucf (12512, 2006-05-08)
rtl_release\rtl (0, 2006-05-09)
rtl_release\rtl\mem_clk_rst.v (6015, 2006-05-09)
rtl_release\rtl\mem_ctrl.v (31925, 2006-05-09)
rtl_release\rtl\mem_io_ctrl.v (1487, 2006-05-09)
rtl_release\rtl\mem_param.v (2758, 2006-05-03)
rtl_release\rtl\mem_phy.v (7549, 2006-05-09)
rtl_release\rtl\mem_phy_calib.v (26858, 2006-05-09)
rtl_release\rtl\mem_phy_ctl_io.v (4902, 2006-05-09)
rtl_release\rtl\mem_phy_dm_iob.v (1164, 2006-05-09)
rtl_release\rtl\mem_phy_dqs_iob.v (3220, 2006-05-09)
rtl_release\rtl\mem_phy_dq_iob.v (4131, 2006-05-09)
rtl_release\rtl\mem_phy_init.v (22304, 2006-05-09)
rtl_release\rtl\mem_phy_io.v (5747, 2006-05-09)
rtl_release\rtl\mem_phy_write.v (6515, 2006-05-09)
rtl_release\rtl\mem_RAM_D.v (4070, 2006-05-09)
rtl_release\rtl\mem_tb_top.v (7125, 2006-05-09)
rtl_release\rtl\mem_test.v (5768, 2006-05-09)
rtl_release\rtl\mem_test_cmp.v (5538, 2006-05-09)
rtl_release\rtl\mem_test_rom.v (5666, 2006-05-09)
rtl_release\rtl\mem_test_rom_addr.v (4509, 2006-05-09)
rtl_release\rtl\mem_test_rom_data.v (7776, 2006-05-09)
rtl_release\rtl\mem_top.v (8761, 2006-05-09)
rtl_release\rtl\mem_usr.v (3506, 2006-05-09)
rtl_release\rtl\mem_usr_ip_addr_fifo.v (3849, 2006-05-09)
rtl_release\rtl\mem_usr_ip_fifos.v (4616, 2006-05-09)
rtl_release\rtl\mem_usr_ip_wr_fifo.v (3976, 2006-05-09)
rtl_release\rtl\mem_usr_rd.v (2518, 2006-05-09)
rtl_release\rtl\mem_usr_rd_fifo.v (5287, 2006-05-09)
rtl_release\sim (0, 2006-05-08)
rtl_release\sim\ddr2.v (100760, 2006-05-08)
rtl_release\sim\mem_interface_top_tb.v (5709, 2006-05-08)

******************************************************************************* ** Copyright (c) 2006 Xilinx, Inc. ** All Rights Reserved ******************************************************************************* ** ____ ____ ** / /\/ / ** /___/ \ / Vendor: Xilinx ** \ \ \/ Version: 1.0 ** \ \ Filename: readme.txt ** / / Timestamp: 8 May 2006 ** /___/ /\ ** \ \ / \ ** \___\/\___\ ** ** ** Device: Virtex-5 ** Purpose: ** High Performance DDR2 SDRAM Interface using SERDES ** ** Reference: ** XAPP858 ******************************************************************************* *************************************************************************************************************** ** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are ** provided to you "as is". Xilinx and its licensors make and you ** receive no warranties or conditions, express, implied, ** statutory or otherwise, and Xilinx specifically disclaims any ** implied warranties of merchantability, non-infringement,or ** fitness for a particular purpose. Xilinx does not warrant that ** the functions contained in these designs will meet your ** requirements, or that the operation of these designs will be ** uninterrupted or error free, or that defects in the Designs ** will be corrected. Furthermore, Xilinx does not warrantor ** make any representations regarding use or the results of the ** use of the designs in terms of correctness, accuracy, ** reliability, or otherwise. ** ** LIMITATION OF LIABILITY. In no event will Xilinx or its ** licensors be liable for any loss of data, lost profits,cost ** or procurement of substitute goods or services, or for any ** special, incidental, consequential, or indirect damages ** arising from the use or operation of the designs or ** accompanying documentation, however caused and on any theory ** of liability. This limitation will apply even if Xilinx ** has been advised of the possibility of such damage. This ** limitation shall apply not-withstanding the failure of the ** essential purpose of any limited remedies herein. ** ** Copyright 2006 Xilinx, Inc. ** All rights reserved ** ************************************************************************************************************** This readme describes how to use the reference design files provided with XAPP858. ************************************************************************************************************** Implementation details: Synthesis - XST Simulation - Modelsim 6.1 SE ISE - 8.2i Placer Effort- set to HIGH ************************************************************************************************************** Readme.txt includes Design hierarchy for DDR2 SDRAM interface based on the ML561 ************************************************************************************************************** The xapp858.zip archive includes the following set of design files: ************************************************************************************************************** HDL files =============== Design Hierarchy for ***-bit DDR2 SDRAM interface: mem_tb_top.v - toplevel file 1. mem_clk_rst.v - instantiates DCM and generates CLK0/CLK90 and instantiates BUFG for 200 MHz reference clock. 2. mem_io_ctrl.v - instantiation of the idela_ctrl primitive reqd. for using the IDELAY block 3. mem_test.v - synthesizable test bench module emulating user application. Instantiates the mem_test_cmp.v and mem_test_rom.v modules. 3.(i) mem_test_cmp.v - compares write vs. read data and generates the Error signal. 3.(ii) mem_test_rom.v - generates the wr/rd addresses and wr data. Instantiates the mem_test_rom_addr.v and mem_test_rom_data.v modules. (ii.1) mem_test_rom_addr.v - generates wr/rd addresses associated with a command request using the RAMB36 primitive as a ROM. (ii.2) mem_test_rom_data.v - generates wr data associated with write request 4. mem_top.v - instantiates the controller, the physical layer, and the user_interface. 4.(i) mem_ctrl.v - DDR2 controller command state machine. 4.(ii) mem_phy.v - physical layer interface comprising read/write data paths, calibration logic, and memory initialization state machine (ii.1) mem_phy_write.v - transmits write data during write operations (ii.2) mem_phy_io.v - instantiates the mem_phy_calib.v, mem_phy_dqs_iob.v, mem_phy_dm_iob.v, and mem_phy_dq_iob.v modules (ii.2.a) mem_phy_calib.v - state machine for aligning DQS and DQ to the FPGA clock (ii.2.b) mem_phy_dqs_iob.v - instantiates the IDELAY and ODDR primitives for DQS signals (ii.2.c) mem_phy_dm_iob.v - instantiates the ODDR primitive for DM signals (ii.2.d) mem_phy_dq_iob.v - instantiates the IDELAY, ISERDES, and ODDR primitives for DQ signals (ii.3) mem_phy_ctl_io.v - implements the muxes for command signals output during calibration versus normal operation (ii.4) mem_phy_init.v - implements the memory initialization state machine 4.(iii)mem_usr.v - interface between the user application and the memory interface (iii.1) mem_usr_rd.v - instantiations of mem_usr_rd_fifo modules (iii.1.a) mem_usr_rd_fifo.v - Distributed RAM instantiations to store rising and falling data output from the ISERDES (iii.2) mem_usr_ip_fifos.v - FIFO instantiations to store write address/data and read address (iii.2.a) mem_usr_ip_addr_fifo.v - Stores read and write addresses in FIFO36 (iii.2.b) mem_usr_ip_wr_fifo.v - Stores write data in FIFO36 mem_param.v - memory parameters required by the design Simulation Files ================== 1. top_tb.v - HDL test bench file 2. ddr2.v - memory model from Micron Other Files =============== - mem_tb_top.ucf - this file includes example timing and location (LOC) constraints for the reference design as implemented on an ML561 memory evaluation board.

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