VerilogHDL_advanced_digital_design_code_Ch4
所属分类：VHDL/FPGA/Verilog
开发工具：Windows_Unix
文件大小：21KB
下载次数：11
上传日期：2007-11-27 10:10:43
上 传 者：
lianlianmao
说明： Verilog HDL 高级数字设计源码 _chapter4
(Advanced Digital Design Verilog HDL source _chapter4)
文件列表:
VerilogHDL_advanced_digital_design_code_Ch 4\ADDVB_Models_4.doc (74752, 2004-10-12)
VerilogHDL_advanced_digital_design_code_Ch 4\Add_rca_4.v (1326, 2000-10-09)
VerilogHDL_advanced_digital_design_code_Ch 4\AOI_str.v (254, 2000-10-12)
VerilogHDL_advanced_digital_design_code_Ch 4\AOI_UDP.v (1234, 2000-10-13)
VerilogHDL_advanced_digital_design_code_Ch 4\compare_2_str.v (421, 2002-08-28)
VerilogHDL_advanced_digital_design_code_Ch 4\compare_4_str.v (1353, 2001-01-10)
VerilogHDL_advanced_digital_design_code_Ch 4\Mux_2_32_CA.v (259, 2002-06-12)
VerilogHDL_advanced_digital_design_code_Ch 4\Mux_4_32_CA.v (450, 2002-06-12)
VerilogHDL_advanced_digital_design_code_Ch 4\Mux_4_32_case.v (562, 2002-06-12)
VerilogHDL_advanced_digital_design_code_Ch 4\Mux_4_32_CA_if.v (567, 2002-06-12)
VerilogHDL_advanced_digital_design_code_Ch 4\test_hiZ.v (694, 2000-10-12)
VerilogHDL_advanced_digital_design_code_Ch 4\t_Add_full_ASIC.v (966, 2002-05-10)
VerilogHDL_advanced_digital_design_code_Ch 4\t_Add_full_unit_delay.v (876, 2002-05-10)
VerilogHDL_advanced_digital_design_code_Ch 4\t_Add_half.v (461, 2000-10-07)
VerilogHDL_advanced_digital_design_code_Ch 4\t_Add_rca_4_Unit_Delay.v (1226, 2000-10-08)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\ADDVB_Models_4.doc (634, 2002-12-30)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\Add_rca_4.v (258, 2000-10-09)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\AOI_str.v (257, 2000-10-12)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\AOI_UDP.v (258, 2000-10-13)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\compare_2_str.v (257, 2002-08-28)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\compare_4_str.v (258, 2001-01-10)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\Mux_2_32_CA.v (257, 2002-06-12)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\Mux_4_32_CA.v (257, 2002-06-12)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\Mux_4_32_case.v (257, 2002-06-12)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\Mux_4_32_CA_if.v (257, 2002-06-12)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\test_hiZ.v (257, 2000-10-12)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\t_Add_full_ASIC.v (257, 2002-05-10)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\t_Add_full_unit_delay.v (257, 2002-05-10)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\t_Add_half.v (257, 2000-10-07)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf\t_Add_rca_4_Unit_Delay.v (258, 2000-10-08)
VerilogHDL_advanced_digital_design_code_Ch 4\_vti_cnf (0, 2007-11-27)
VerilogHDL_advanced_digital_design_code_Ch 4 (0, 2007-11-27)
近期下载者：
相关文件：
收藏者：