vhdlsource
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：4KB
下载次数：42
上传日期：2007-11-30 15:56:27
上 传 者：
thelark
说明： 用verilog hdl编写的一些例程，包括加法器/减法器等等，例子较多就不一一列举了
(Verilog hdl prepared with some routines, including the adder/subtraction, etc., for example, more is not to enumerate the)
文件列表:
vhdlsource\add4_1.v (305, 2003-12-04)
vhdlsource\add4_2.v (134, 2003-11-25)
vhdlsource\add4_3.v (192, 2003-12-04)
vhdlsource\count4.v (181, 2003-12-04)
vhdlsource\full_add1.v (208, 2003-12-04)
vhdlsource\full_add2.v (155, 2003-12-04)
vhdlsource\full_add3.v (110, 2003-11-25)
vhdlsource\full_add4.v (236, 2003-12-04)
vhdlsource\full_add5.v (373, 2003-11-25)
vhdlsource\half_add1.v (107, 2003-12-04)
vhdlsource\half_add2.v (109, 2003-11-25)
vhdlsource\half_add3.v (313, 2003-12-04)
vhdlsource\half_add4.v (143, 2003-12-04)
vhdlsource\mux2_1a.v (140, 2003-12-04)
vhdlsource\mux2_1b.v (161, 2003-12-04)
vhdlsource\mux2_1c.v (97, 2003-12-04)
vhdlsource\mux4_1a.v (334, 2003-12-04)
vhdlsource\mux4_1b.v (296, 2003-12-04)
vhdlsource\mux4_1c.v (236, 2003-12-04)
vhdlsource\mux4_1d.v (174, 2003-12-04)
vhdlsource (0, 2007-11-30)
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