fpga_HDL.examples
所属分类：VHDL/FPGA/Verilog
开发工具：IDL
文件大小：106KB
下载次数：65
上传日期：2007-12-05 18:31:19
上 传 者：
chnmy
说明： 多个Verilog和vhdl程序例子，可以作为初学者参考实例，按照电路结构写出HDL代码
(A number of examples of Verilog and VHDL program can be used as reference examples for beginners, in accordance with the circuit structure to write HDL code)
文件列表:
examples\stderr.log (0, 2007-01-05)
examples\stdout.log (0, 2007-01-05)
examples\synhooks_for_vif2conformal.tcl (1694, 2007-01-05)
examples\tcl\synhooks\synhooks.tcl (4646, 2007-01-05)
examples\tcl\synhooks\synhooks_for_vif2conformal.tcl (1742, 2007-01-05)
examples\tcl\tcl_find\analyze_netlist_clocks.tcl (7088, 2007-01-05)
examples\tcl\tcl_find\comb_fanout_gt_8_altera.txt (484, 2007-01-05)
examples\tcl\tcl_find\feedthrough_altera.txt (576, 2007-01-05)
examples\tcl\tcl_find\find_lut3_xilinx.txt (381, 2007-01-05)
examples\tcl\tcl_find\slack_gt_2_xilinx.txt (473, 2007-01-05)
examples\verilog\actel\prep2_2.prj (662, 2007-01-05)
examples\verilog\actel\prep2_2.sdc (407, 2007-01-05)
examples\verilog\altera\prep2_2.prj (488, 2007-01-05)
examples\verilog\altera\prep2_2.sdc (390, 2007-01-05)
examples\verilog\altera\rtl\adder8.v (850, 2007-01-05)
examples\verilog\altera\rtl\myramv.v (340, 2007-01-05)
examples\verilog\altera\rtl\ram64x16.v (909, 2007-01-05)
examples\verilog\altera\rtl\sqrterr.v (1148, 2007-01-05)
examples\verilog\common_rtl\combinat\adder.v (350, 2007-01-05)
examples\verilog\common_rtl\combinat\adder16.v (412, 2007-01-05)
examples\verilog\common_rtl\combinat\adder8.v (210, 2007-01-05)
examples\verilog\common_rtl\combinat\adder_8.v (191, 2007-01-05)
examples\verilog\common_rtl\combinat\alu.v (565, 2007-01-05)
examples\verilog\common_rtl\combinat\bitand.v (210, 2007-01-05)
examples\verilog\common_rtl\combinat\compare.v (163, 2007-01-05)
examples\verilog\common_rtl\combinat\decoder.v (124, 2007-01-05)
examples\verilog\common_rtl\combinat\encoder1.v (404, 2007-01-05)
examples\verilog\common_rtl\combinat\encoder2.v (462, 2007-01-05)
examples\verilog\common_rtl\combinat\encoder3.v (596, 2007-01-05)
examples\verilog\common_rtl\combinat\mux.v (164, 2007-01-05)
examples\verilog\common_rtl\combinat\mux1.v (131, 2007-01-05)
examples\verilog\common_rtl\combinat\mux2.v (404, 2007-01-05)
examples\verilog\common_rtl\combinat\mux3.v (387, 2007-01-05)
examples\verilog\common_rtl\combinat\parity.v (223, 2007-01-05)
examples\verilog\common_rtl\combinat\sort4.v (881, 2007-01-05)
examples\verilog\common_rtl\combinat\sqrt.v (599, 2007-01-05)
examples\verilog\common_rtl\combinat\tristate.v (531, 2007-01-05)
examples\verilog\common_rtl\dsp\accum.v (367, 2007-01-05)
examples\verilog\common_rtl\dsp\addmult.v (447, 2007-01-05)
examples\verilog\common_rtl\memory\ram_1.v (394, 2007-01-05)
... ...
近期下载者：
相关文件：
收藏者：