mem_ctrl.tar
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：324KB
下载次数：158
上传日期：2007-12-11 21:56:15
上 传 者：
youjia1983
说明： verilog 写的 memory controller ，可以控制SDRAM SRAM NOR
(written in Verilog memory controller, can control SDRAM SRAM NOR)
文件列表:
mem_ctrl (0, 2007-03-12)
mem_ctrl\CVS (0, 2007-03-12)
mem_ctrl\CVS\Root (13, 2007-03-12)
mem_ctrl\CVS\Repository (9, 2007-03-12)
mem_ctrl\CVS\Entries (52, 2007-03-12)
mem_ctrl\bench (0, 2007-03-12)
mem_ctrl\bench\CVS (0, 2007-03-12)
mem_ctrl\bench\CVS\Root (13, 2007-03-12)
mem_ctrl\bench\CVS\Repository (15, 2007-03-12)
mem_ctrl\bench\CVS\Entries (39, 2007-03-12)
mem_ctrl\bench\richard (0, 2007-03-12)
mem_ctrl\bench\richard\CVS (0, 2007-03-12)
mem_ctrl\bench\richard\CVS\Root (13, 2007-03-12)
mem_ctrl\bench\richard\CVS\Repository (23, 2007-03-12)
mem_ctrl\bench\richard\CVS\Entries (14, 2007-03-12)
mem_ctrl\bench\richard\verilog (0, 2007-03-12)
mem_ctrl\bench\richard\verilog\CVS (0, 2007-03-12)
mem_ctrl\bench\richard\verilog\CVS\Root (13, 2007-03-12)
mem_ctrl\bench\richard\verilog\CVS\Repository (31, 2007-03-12)
mem_ctrl\bench\richard\verilog\CVS\Entries (415, 2007-03-12)
mem_ctrl\bench\richard\verilog\bench.v (12649, 2002-03-06)
mem_ctrl\bench\richard\verilog\checkers.v (5914, 2002-03-06)
mem_ctrl\bench\richard\verilog\mc_defines.v (8312, 2002-03-06)
mem_ctrl\bench\richard\verilog\timescale.v (23, 2002-03-06)
mem_ctrl\bench\richard\verilog\tst_asram.v (8843, 2002-03-06)
mem_ctrl\bench\richard\verilog\tst_multi_mem.v (18871, 2002-03-06)
mem_ctrl\bench\richard\verilog\tst_sdram.v (45455, 2002-03-06)
mem_ctrl\bench\richard\verilog\tst_ssram.v (6331, 2002-03-06)
mem_ctrl\bench\richard\verilog\wb_master_model.v (9469, 2002-03-06)
mem_ctrl\bench\richard\verilog\models (0, 2007-03-12)
mem_ctrl\bench\richard\verilog\models\CVS (0, 2007-03-12)
mem_ctrl\bench\richard\verilog\models\CVS\Root (13, 2007-03-12)
mem_ctrl\bench\richard\verilog\models\CVS\Repository (38, 2007-03-12)
mem_ctrl\bench\richard\verilog\models\CVS\Entries (136, 2007-03-12)
mem_ctrl\bench\richard\verilog\models\m8kx8.v (7052, 2002-03-06)
mem_ctrl\bench\richard\verilog\models\mt48lc16m16a2.v (48522, 2002-03-06)
mem_ctrl\bench\richard\verilog\models\mt58l1my18d.v (9360, 2002-03-06)
mem_ctrl\bench\verilog (0, 2007-03-12)
mem_ctrl\bench\verilog\CVS (0, 2007-03-12)
mem_ctrl\bench\verilog\CVS\Root (13, 2007-03-12)
... ...
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