alaw_mulaw
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：61KB
下载次数：37
上传日期：2007-12-23 13:21:07
上 传 者：
liudongpei
说明： 这是一个量化编码当中关于A律和u律压缩和扩展的源程序，程序由VerilogHDL语言编写，算法在Modelsim上进行仿真过
(This is a quantization coding of them on the A law and u law compression and expansion of the source code, the program by VerilogHDL languages, algorithms in the ModelSim simulation have been carried out)
文件列表:
alaw_mulaw\a-law_compression.cr.mti (2, 2007-05-29)
alaw_mulaw\a-law_compression.mpf (19753, 2007-05-29)
alaw_mulaw\int2alaw.v (1387, 2007-05-29)
alaw_mulaw\linear2ulaw.v (1131, 2007-05-25)
alaw_mulaw\sim_linear2ulaw.v (560, 2007-05-25)
alaw_mulaw\test_int2alaw(05-29).txt (688126, 2007-05-29)
alaw_mulaw\test_int2alaw.v (497, 2007-05-29)
alaw_mulaw\test_ulaw2int(5-29).txt (18174, 2007-05-29)
alaw_mulaw\test_ulaw2int.v (501, 2007-05-29)
alaw_mulaw\transcript (444, 2007-11-29)
alaw_mulaw\u-law_expansion.cr.mti (2, 2007-05-29)
alaw_mulaw\u-law_expansion.mpf (20154, 2007-05-29)
alaw_mulaw\ulaw2int.v (976, 2007-05-29)
alaw_mulaw\work\int2alaw\verilog.asm (9352, 2007-05-29)
alaw_mulaw\work\int2alaw\_primary.dat (1231, 2007-05-29)
alaw_mulaw\work\int2alaw\_primary.vhd (260, 2007-05-29)
alaw_mulaw\work\test_int2alaw\verilog.asm (6054, 2007-05-29)
alaw_mulaw\work\test_int2alaw\_primary.dat (521, 2007-05-29)
alaw_mulaw\work\test_int2alaw\_primary.vhd (86, 2007-05-29)
alaw_mulaw\work\test_ulaw2int\verilog.asm (6062, 2007-05-29)
alaw_mulaw\work\test_ulaw2int\_primary.dat (526, 2007-05-29)
alaw_mulaw\work\test_ulaw2int\_primary.vhd (86, 2007-05-29)
alaw_mulaw\work\ulaw2int\verilog.asm (7479, 2007-05-29)
alaw_mulaw\work\ulaw2int\_primary.dat (1218, 2007-05-29)
alaw_mulaw\work\ulaw2int\_primary.vhd (260, 2007-05-29)
alaw_mulaw\work\_info (767, 2007-05-29)
alaw_mulaw\work\int2alaw (0, 2007-12-23)
alaw_mulaw\work\test_int2alaw (0, 2007-12-23)
alaw_mulaw\work\test_ulaw2int (0, 2007-12-23)
alaw_mulaw\work\ulaw2int (0, 2007-12-23)
alaw_mulaw\work (0, 2007-12-23)
alaw_mulaw (0, 2007-12-23)
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