文件列表:

manual_430.pdf (334166, 2000-03-27)
manual_430.ps (1399938, 2000-03-27)
t-vpack (0, 2000-03-27)
t-vpack\cluster.c (55809, 2000-03-26)
t-vpack\cluster.h (637, 2000-03-26)
t-vpack\descript.txt (7350, 2000-03-26)
t-vpack\e64.blif (11784, 2000-03-26)
t-vpack\ff_pack.c (6883, 2000-03-26)
t-vpack\ff_pack.h (150, 2000-03-26)
t-vpack\globals.h (266, 2000-03-26)
t-vpack\heapsort.c (3109, 2000-03-26)
t-vpack\heapsort.h (65, 2000-03-26)
t-vpack\main.c (19951, 2000-03-26)
t-vpack\makefile (2343, 2000-03-26)
t-vpack\output_clustering.c (18341, 2000-03-26)
t-vpack\output_clustering.h (285, 2000-03-26)
t-vpack\path_length.c (48786, 2000-03-26)
t-vpack\path_length.h (889, 2000-03-26)
t-vpack\read_blif.c (20150, 2000-03-26)
t-vpack\read_blif.h (115, 2000-03-26)
t-vpack\s1423.blif (12642, 2000-03-26)
t-vpack\util.c (15822, 2000-03-26)
t-vpack\util.h (3132, 2000-03-26)
t-vpack\vpack.h (1762, 2000-03-26)
vpr (0, 2000-03-27)
vpr\4lut_sanitized.arch (2098, 2000-03-26)
vpr\4x4lut_sanitized.arch (3064, 2000-03-26)
vpr\check_netlist.c (18470, 2000-03-26)
vpr\check_netlist.h (74, 2000-03-26)
vpr\check_route.c (20231, 2000-03-26)
vpr\check_route.h (116, 2000-03-26)
vpr\check_rr_graph.c (16277, 2000-03-26)
vpr\check_rr_graph.h (129, 2000-03-26)
vpr\descript.txt (33193, 2000-03-27)
vpr\draw.c (44183, 2000-03-26)
vpr\draw.h (316, 2000-03-26)
vpr\e64-4lut.net (33974, 2000-03-26)
vpr\e64-4x4lut.net (22107, 2000-03-26)
vpr\globals.h (1257, 2000-03-26)
... ...

This archive contains VPR, an FPGA placement and routing tool, and T-VPack, a program to pack LUTs and flip flops into coarser grained logic blocks and convert a netlist from blif format to VPR's .net format. There is a detailed manual covering everything from how to compile the programs to how to use them in manual_430.ps (and manual_430.pdf if you prefer .pdf format). To see VPR in action on the (small) sample circuit (e*** from the MCNC benchmark suite) and the sample FPGA architecture files type: cd vpr (if not already there) vpr e***-4x4lut.net 4x4lut_sanitized.arch e***.p e***.r -route_chan_width 40 -inner_num 3 (Add -nodisp to the command line above if you're not running on an X-Windows graphics capable computer.) The logic block for this architecture contains 4, 4-input look-up tables and 4 flip flops along with local routing (a cluster-based logic block of size 4). The routing wire segments all span 4 logic blocks in this architecture. I've also included a simpler architecture in which a logic block is only a 4 LUT plus a flip flop, and in which all routing wires span only one logic block. To run this case, try: cd vpr (if not already there) vpr e***-4lut.net 4lut_sanitized.arch e***.p e***.r -route_chan_width 10 -inner_num 3 The two netlists (e***-4x4lut.net and e***-4lut.net) were created using T-VPack on a technology-mapped netlist in .blif format, with the appropriate options in each case: cd t-vpack (if not already there) t-vpack e***.blif e***-4x4lut.net -cluster_size 4 -inputs_per_cluster 10 and cd t-vpack (if not already there) t-vpack e***.blif e***-4lut.net -no_clustering There are a lot of different ways to use VPR and T-VPack -- see manual_430.ps or manual_430.pdf for details. -- Vaughn Betz, March 25, 2000 ============================================================================== Contents of the archive: README_430.txt: This file. manual_430.ps: Postscript manual of VPR and T-VPack. manual_430.pdf: PDF version of the manual. ./vpr *.c, *.h: Source code for VPR. makefile: Makefile for VPR. Currently set for Solaris and gcc; you may have to modify the library paths and compiler options on your machine. descript.txt: A revision history of VPR. e***-4x4lut.net: A sample netlist file from the MCNC bencmark set. The logic block contains 4 4-input LUTs and 4 FFs. e***-4lut.net: A sample netlist file from the MCNC benchmark set. The logic block contains 1 4-LUT and 1 FF. 4x4lut_sanitized.arch: A sample FPGA architecture file, with a logic block containing 4 4-input LUTs and 4 FFs. 4lut_sanitized.arch: A sample FPGA architecture file, with a logic block containing 1 4-LUT and 1 FF. ./vpack *.c, *.h: Source code for T-VPack. makefile: Makefile for T-VPack. May have to be modified for non Solaris machines or for compilers other than gcc. descript.txt: Revision history of VPack / T-VPack. e***.blif: MCNC benchmark circuit e*** technology-mapped by Flowmap to 4-input LUTs. This is a combinational circuit. s1423.blif: A sequential MCNC benchmark circuit. It has been technology- mapped to 4-input LUTs and flip flops by Flowmap. ============================================================================== Major changes from VPR Version 4.22 to this Version (4.30), and from VPack Version 2.09 to T-VPack Version 4.30 are: 1) VPack has been made timing-driven, and it's name has been changed to T-VPack. It can still be run in the old, non-timing driven mode (specify -timing_driven off), but the timing-driven algorithm gets better timing and routability than the old algorithm. The timing-driven packing algorithm is used by default. Sandy Marquardt wrote the new, timing-driven algorithm in T-VPack. 2) The VPR placer algorithm has been made timing-driven, again by Sandy Marquardt. The timing-driven mode is the default. Running the placer in timing-driven mode speeds up the typical circuit by about 25% while only costing about 5% more routing.

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