RSverilog
所属分类：SCSI/ASPI
开发工具：Others
文件大小：2304KB
下载次数：228
上传日期：2007-12-27 13:02:31
上 传 者：
刘琼1981
说明： RS编码的verilog源代码，拿来和大家分享
(RS-coded Verilog source code, used to share)
文件列表:
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\adderror_test.vwf (5390, 2007-06-12)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\Clock.bsf (1765, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\Clock.v (159, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\common_modules.v (2515, 2007-06-05)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\CSEEBLOCK.v (9362, 2007-06-05)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\DEcontroller.v (17008, 2007-05-20)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\error.bsf (1582, 2007-06-12)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\error.v (268, 2007-06-13)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\fifo_register.v (3154, 2007-06-05)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\frequency divider.v (1590, 2007-05-31)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\KESBLOCK.V (12692, 2007-06-05)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\nrz.bsf (2134, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\pll.bsf (3412, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\pll.cmp (962, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\pll.v (9475, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\Pll_57Mto31M.v (9505, 2007-05-29)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\pll_57_31.v (9502, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\pll_bb.v (8000, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\pll_wave0.jpg (75721, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\pll_waveforms.html (887, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\RAM.v (1814, 2007-05-18)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\RAM_fifo_all.v (6042, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\rs.bdf (26346, 2007-06-12)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\rs.vwf (38817, 2007-06-12)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\rsdecode.v (4977, 2007-06-03)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\RSDecoder.bsf (5923, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\RSDecoder.v (2069, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\rsencode.v (2360, 2007-12-25)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\RSEncoder.bsf (4197, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\RSEncoder.v (1580, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\RS_encode_and_decode.qpf (897, 2007-05-15)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\RS_encode_and_decode.qws (1686, 2007-06-13)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\SCBLOCK.V (10615, 2007-06-05)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\serial_paralled_conversion.v (1699, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\source_nrz.v (800, 2007-06-11)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\top.asm.rpt (7598, 2007-06-13)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\top.cdf (279, 2007-06-12)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\top.done (26, 2007-06-13)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\top.dpf (121, 2007-06-12)
RS_19_31_EP1C6Q240_TEST verilog\RS_19_31_EP1C6Q240_TEST2\top.fit.eqn (452500, 2007-06-13)
... ...
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