VerilogHDL
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：980KB
下载次数：20
上传日期：2007-12-27 20:50:32
上 传 者：
jzhupo
说明： 《设计与验证Verilog HDL》光盘内容
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文件列表:
设计与验证Verilog HDL\Example-7-1\示例说明.doc (20992, 2006-06-01)
设计与验证Verilog HDL\Example-7-2\示例说明.doc (20992, 2006-06-01)
设计与验证Verilog HDL\Example-7-3\示例说明.doc (20992, 2006-06-01)
设计与验证Verilog HDL\Example-7-4\示例说明.doc (20992, 2006-06-01)
设计与验证Verilog HDL\Example-8-1\示例说明.doc (20992, 2006-06-01)
设计与验证Verilog HDL\Example-8-2\示例说明.doc (21504, 2006-06-01)
设计与验证Verilog HDL\Example-4-10\示例说明.doc (22528, 2006-06-01)
设计与验证Verilog HDL\Example-5-6\示例说明.doc (22528, 2006-06-01)
设计与验证Verilog HDL\Example-5-7\示例说明.doc (22528, 2006-06-01)
设计与验证Verilog HDL\Example-5-8\示例说明.doc (22528, 2006-06-01)
设计与验证Verilog HDL\Example-4-13\示例说明.doc (23040, 2006-06-01)
设计与验证Verilog HDL\Example-4-16\示例说明.doc (23040, 2006-06-01)
设计与验证Verilog HDL\Example-4-11\示例说明.doc (23552, 2006-06-01)
设计与验证Verilog HDL\Example-4-20\示例说明.doc (23552, 2006-06-01)
设计与验证Verilog HDL\Example-4-7\示例说明.doc (23552, 2006-06-01)
设计与验证Verilog HDL\Example-4-8\示例说明.doc (23552, 2006-06-01)
设计与验证Verilog HDL\Example-5-1\示例说明.doc (23552, 2006-06-01)
设计与验证Verilog HDL\Example-5-5\示例说明.doc (23552, 2006-06-01)
设计与验证Verilog HDL\Example-4-1\示例说明.doc (25088, 2006-06-01)
设计与验证Verilog HDL\Example-4-14\示例说明.doc (25088, 2006-06-01)
设计与验证Verilog HDL\Example-4-4\示例说明.doc (25088, 2006-06-01)
设计与验证Verilog HDL\Example-4-17\示例说明.doc (26112, 2006-06-01)
设计与验证Verilog HDL\Example-4-21\示例说明.doc (28160, 2006-06-01)
设计与验证Verilog HDL\Example-6-1\示例说明.doc (31232, 2006-06-01)
设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\CS.txt (1296, 2005-12-16)
设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\CS.txt (1296, 2005-12-16)
设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\CS.txt (1296, 2005-12-16)
设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\NS.txt (1296, 2005-12-16)
设计与验证Verilog HDL\Example-7-2\Proj\Read_In_File.txt (430, 2005-12-19)
设计与验证Verilog HDL\Example-7-3\Proj\Read_In_File.txt (430, 2005-12-19)
设计与验证Verilog HDL\Example-7-4\Proj\Read_In_File.txt (430, 2005-12-19)
设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\unfolded_operators.txt (0, 2006-01-16)
设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\unfolded_operators.txt (0, 2006-01-16)
设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\unfolded_operators.txt (0, 2006-01-16)
设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\unfolded_operators.txt (0, 2006-01-16)
设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\unfolded_operators.txt (0, 2006-01-16)
设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\unfolded_operators.txt (0, 2006-01-16)
设计与验证Verilog HDL\Example-4-10\bibus\rev_1\rpt_bibus_areasrr.htm (5095, 2006-01-02)
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