uart_rx
所属分类：嵌入式/单片机/硬件编程
开发工具：Others
文件大小：521KB
下载次数：109
上传日期：2008-01-10 21:34:29
上 传 者：
celehome
说明： actel A3P250 fpga用VERILOG HDL语言实现串口功能的源代码
(actel A3P250 fpga with VERILOG HDL Serial functional language source code)
文件列表:
uart_rx (0, 2007-09-05)
uart_rx\uart_rx.prj (3916, 2007-09-06)
uart_rx\viewdraw (0, 2007-09-05)
uart_rx\viewdraw\wir (0, 2007-09-05)
uart_rx\viewdraw\vf (0, 2007-09-05)
uart_rx\viewdraw\vf\project.lst (49, 2007-09-06)
uart_rx\viewdraw\sym (0, 2007-09-05)
uart_rx\viewdraw\sch (0, 2007-09-05)
uart_rx\viewdraw\viewdraw.ini (1644, 2007-09-06)
uart_rx\synthesis (0, 2007-09-05)
uart_rx\synthesis\.recordref (0, 2007-06-11)
uart_rx\synthesis\rcvr.areasrr (2299, 2007-06-11)
uart_rx\synthesis\rcvr.edn (69970, 2007-06-11)
uart_rx\synthesis\rcvr.map (0, 2007-06-11)
uart_rx\synthesis\rcvr.sdf (24164, 2007-06-11)
uart_rx\synthesis\rcvr.srd (37643, 2007-06-11)
uart_rx\synthesis\rcvr.srm (231115, 2007-06-11)
uart_rx\synthesis\rcvr.srr (21691, 2007-06-11)
uart_rx\synthesis\rcvr.srs (6068, 2007-06-11)
uart_rx\synthesis\rcvr.tlg (1062, 2007-06-11)
uart_rx\synthesis\rcvr_sdc.sdc (310, 2007-06-11)
uart_rx\synthesis\stdout.log (6568, 2007-06-11)
uart_rx\synthesis\traplog.tlg (4325, 2007-06-11)
uart_rx\synthesis\syntmp (0, 2007-09-05)
uart_rx\synthesis\syntmp\rcvr.msg (1083, 2007-06-11)
uart_rx\synthesis\syntmp\rcvr.plg (647, 2007-06-11)
uart_rx\synthesis\rcvr_syn.prj (407, 2007-09-06)
uart_rx\stimulus (0, 2007-09-05)
uart_rx\smartgen (0, 2007-09-05)
uart_rx\smartgen\smartgen.aws (366, 2007-09-06)
uart_rx\simulation (0, 2007-09-05)
uart_rx\simulation\modelsim.ini.sav (225, 2007-09-06)
uart_rx\simulation\modelsim.ini (227, 2007-09-06)
uart_rx\simulation\meminit.dat (2816, 2007-09-06)
uart_rx\phy_synthesis (0, 2007-09-05)
uart_rx\hdl (0, 2007-09-05)
uart_rx\hdl\rcvr.v (4831, 2007-06-11)
uart_rx\hdl\waveperl.log (0, 2007-09-05)
uart_rx\designer (0, 2007-09-05)
uart_rx\designer\impl1 (0, 2007-09-05)
... ...
近期下载者：
相关文件：
收藏者：