文件列表:

vhdl (0, 2002-10-08)
vhdl\func_sim (0, 2002-10-08)
vhdl\func_sim\brst_cntr.vhd (1003, 2000-11-02)
vhdl\func_sim\cslt_cntr.vhd (1060, 2000-11-02)
vhdl\func_sim\ki_cntr.vhd (1085, 2000-11-02)
vhdl\func_sim\load.do (407, 2000-11-02)
vhdl\func_sim\mt48lc1m16a1.v (36273, 2000-11-02)
vhdl\func_sim\mti_pkg.vhd (4781, 2000-11-02)
vhdl\func_sim\rcd_cntr.vhd (1111, 2000-11-02)
vhdl\func_sim\ref_cntr.vhd (1077, 2000-11-02)
vhdl\func_sim\run_sim.do (357, 2000-11-02)
vhdl\func_sim\sdrm.vhd (16925, 2000-11-02)
vhdl\func_sim\sdrmc_state.vhd (5461, 2000-11-02)
vhdl\func_sim\sdrm_t.vhd (7245, 2000-11-02)
vhdl\func_sim\state.do (329, 2000-11-02)
vhdl\func_sim\sys_int.vhd (6897, 2000-11-02)
vhdl\func_sim\tb_sdrm.v (8160, 2000-11-02)
vhdl\func_sim\transcript (10034, 2000-11-02)
vhdl\func_sim\verwave.do (13899, 2000-11-02)
vhdl\func_sim\work (0, 2002-10-08)
vhdl\func_sim\work\brst_cntr (0, 2002-10-08)
vhdl\func_sim\work\brst_cntr\brst_cntr_arch.asm (3744, 2000-11-02)
vhdl\func_sim\work\brst_cntr\brst_cntr_arch.dat (600, 2000-11-02)
vhdl\func_sim\work\brst_cntr\_primary.dat (308, 2000-11-02)
vhdl\func_sim\work\cslt_cntr (0, 2002-10-08)
vhdl\func_sim\work\cslt_cntr\cslt_cntr_arch.asm (3408, 2000-11-02)
vhdl\func_sim\work\cslt_cntr\cslt_cntr_arch.dat (658, 2000-11-02)
vhdl\func_sim\work\cslt_cntr\_primary.dat (319, 2000-11-02)
vhdl\func_sim\work\ki_cntr (0, 2002-10-08)
vhdl\func_sim\work\ki_cntr\ki_cntr_arch.asm (3424, 2000-11-02)
vhdl\func_sim\work\ki_cntr\ki_cntr_arch.dat (648, 2000-11-02)
vhdl\func_sim\work\ki_cntr\_primary.dat (311, 2000-11-02)
vhdl\func_sim\work\mt48lc1m16a1 (0, 2002-10-08)
vhdl\func_sim\work\mt48lc1m16a1\verilog.asm (189872, 2000-11-02)
vhdl\func_sim\work\mt48lc1m16a1\_primary.dat (19608, 2000-11-02)
vhdl\func_sim\work\mt48lc1m16a1\_primary.vhd (1209, 2000-11-02)
vhdl\func_sim\work\mti_pkg (0, 2002-10-08)
vhdl\func_sim\work\mti_pkg\body.asm (10576, 2000-11-02)
vhdl\func_sim\work\mti_pkg\body.dat (1931, 2000-11-02)
vhdl\func_sim\work\mti_pkg\_primary.dat (351, 2000-11-02)
... ...

---------------------------------------------------------------------------- Log: 1.11 Mujtaba Hamid, 11/1/2000 - Published VHDL version ---------------------------------------------------------------------------- ====================== = Design Description = ====================== The SDRAM controller is designed for the Virtex V300bg432-6. It's simulated with Micron SDRAM models. The design is verified with timing constraints at 115 MHZ. ==================== = Design Hierarchy = ==================== sdrm (top level) sys_int (system interface) sdrm_t (SDRAM controller) sdrmc_state (state machine) brst_cntr (burst counter) rcd_cntr (ras-cas-delay counter) ref_cntr (refresh counter) cslt_cntr (cas-latency counter) ki_cntr (keep-idle-during-refresh-active counter) ================= = Design Notes = ================= DLL: (in sdrm module) ---- . dll0: use for clock mirror, provide the clock for the external SDRAM . dll1: use for deskewing clock signal inside the FPGA (Clk_j), also provide clk2x (Clk_i) Use global clock buffers for clock signals: ------------------------------------------- . There are 4 BUFGPs in Virtex. They provide low-skew high-fanout routings. Use LUT Shift Register to delay signals by certain number of clock cycles -------------------------------------------------------------------------- . delay DLL lock signal (in sdrm_t module) . delay data (in sys_int module) Registering all inputs and ouputs to SDRAM: (in sdrm module) ------------------------------------------- . All signals going to the SDRAM are registered in the IOB This makes it easy to calculate timings b/t the FPGA and SDRAM For write cycles, add FPGA Tiockp to SDRAM Tsu For read cycles, add SDRAM Tac to FPGA Tsu and . The tristate signal for the data lines are also registered in the IOB . Instead of 1 tristate signal for the Data lines, we duplicate it to 4 signals, each having 8 loads. This was done to reduce net delays on that tristate signal. The tristate signal is sd_doe_n in sdrm Use fast output buffers: (in sdrm module) ------------------------ . IOBUF_F_12: all signals interfacing to SDRAM These may create more bounce but are ~2ns faster than regular OBUFs Use NODELAY mode for input buffers: (in ucf constraint file) ----------------------------------- . The default IBUF has additional delay to give negative hold time. This eliminates pad-to-pad hold time . Set NODELAY attribute on inputs to reduce IBUF delay by about 1.5ns Set timing constraints for place & route tool: (in ucf constraint file) --------------------------------------------- . set clock period on input clock (Clkp) . set periods b/t clk1x and clk2x (Clk_j, Clk_i) . set OFFSET constraint for inputs and outputs ================ = Instructions = ================ . to run functional simulation (with MTI): cd func_sim run_sim.do . to compile the design (with Synplify): cd synth Open vhdl.prj file Click on the "run" button . to run backannotated simulation: cd post_route run_sim.do ============================== = Frequently asked questions = ============================== 1. Is RAS to CAS delay programmable? ------------------------------------ . No, the data registers has a fixed number of pipeline stages. This reference design supports RAS-to-CAS delay of 2 clock cycles. If you need to adjust to a different RAS-to-CAS delay, change the SRL16 Address values in sys_int.v. The address value should be (Trcd/Tck) +1 . Note, you still need to write the RAS-to-CAS value to the Controller's Mode Reg during PRECHARGE command. The value should be (Trcd/Tck) -2 2. How do I modify the design to support 128Mb/256Mb SDRAM parts with a ***-bit data bus? ---------------------------------------------------------------------------------------- . You'll need to add more IO buffers for the extra data and address signals (in sdrm.v) . You'll need to change ADDR_MSB and DATA_MSB (in define.v) . In the current design, instead of 1 tristate signal for the Data lines, we duplicate it to 4 signals, each having 8 loads. This was done to reduce net delays on that tristate signal. You may need to add 4 more tristate lines if you're going to ***-bit. The tristate signal is sd_doe_n in sdrm.v ========= = files = ========= vhdl: README src/ brst_cntr.vhd cslt_cntr.vhd define.vhd ki_cntr.vhd sys_int.vhd rcd_cntr.vhd ref_cntr.vhd sdrm.vhd sdrm_t.vhd sdrmc_state.vhd micron/ SDRAM model from micron mt48lc1m16a1-8a.v func_sim/ functional simulation tb_sdrm.v test bench run_sim.do script to run verilog synth/ synthesis rev_1 synplicity project directory sdrm.edf synthesized netlist vhdl.prj synplicity project file. par/ place & route sdrm.ucf constraint file sdrm.edf link to ../synth/sdrm.edf (edif netlist) xproj xilinx project direction post_route/ backannotated simulation run_sim.do script to run verilog simulation time_sim.vhd back-annotated structural netlist time_sim.*** SDF file tb_post_route.v test bench

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