dpll_demo
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：66KB
下载次数：329
上传日期：2008-01-19 14:36:03
上 传 者：
donnlu
说明： 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图
(A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform)
文件列表:
dpll_20071023\DPLL.cr.mti (1449, 2007-10-31)
dpll_20071023\DPLL.mpf (45909, 2007-10-31)
dpll_20071023\dpll.v (1843, 2007-10-25)
dpll_20071023\dpll.v.bak (1843, 2007-10-25)
dpll_20071023\dpll_tb.v (484, 2007-10-25)
dpll_20071023\dpll_tb.v.bak (484, 2007-10-25)
dpll_20071023\FFD.v (243, 2007-10-24)
dpll_20071023\id_counter.v (1425, 2007-10-25)
dpll_20071023\JK.v (238, 2007-10-25)
dpll_20071023\k_counter.v (1212, 2007-10-24)
dpll_20071023\transcript (2201, 2007-11-01)
dpll_20071023\vsim.wlf (32768, 2007-10-25)
dpll_20071023\work\@d@p@l@l\verilog.asm (11404, 2007-10-25)
dpll_20071023\work\@d@p@l@l\_primary.dat (1316, 2007-10-25)
dpll_20071023\work\@d@p@l@l\_primary.dbs (3311, 2007-10-25)
dpll_20071023\work\@d@p@l@l\_primary.vhd (361, 2007-10-25)
dpll_20071023\work\@f@f@d\verilog.asm (3551, 2007-10-25)
dpll_20071023\work\@f@f@d\_primary.dat (268, 2007-10-25)
dpll_20071023\work\@f@f@d\_primary.dbs (643, 2007-10-25)
dpll_20071023\work\@f@f@d\_primary.vhd (297, 2007-10-25)
dpll_20071023\work\@j@k\verilog.asm (4567, 2007-10-25)
dpll_20071023\work\@j@k\_primary.dat (314, 2007-10-25)
dpll_20071023\work\@j@k\_primary.dbs (780, 2007-10-25)
dpll_20071023\work\@j@k\_primary.vhd (338, 2007-10-25)
dpll_20071023\work\dpll_tb\verilog.asm (6435, 2007-10-25)
dpll_20071023\work\dpll_tb\_primary.dat (502, 2007-10-25)
dpll_20071023\work\dpll_tb\_primary.dbs (928, 2007-10-25)
dpll_20071023\work\dpll_tb\_primary.vhd (74, 2007-10-25)
dpll_20071023\work\id_counter\verilog.asm (8558, 2007-10-25)
dpll_20071023\work\id_counter\_primary.dat (1438, 2007-10-25)
dpll_20071023\work\id_counter\_primary.dbs (3142, 2007-10-25)
dpll_20071023\work\id_counter\_primary.vhd (311, 2007-10-25)
dpll_20071023\work\k_counter\verilog.asm (7890, 2007-10-25)
dpll_20071023\work\k_counter\_primary.dat (930, 2007-10-25)
dpll_20071023\work\k_counter\_primary.dbs (1731, 2007-10-25)
dpll_20071023\work\k_counter\_primary.vhd (414, 2007-10-25)
dpll_20071023\work\_info (1261, 2007-10-25)
dpll_20071023\work\_opt\vopt0stzyk (74, 2007-10-24)
dpll_20071023\work\_opt\vopt2s8k0n (3142, 2007-10-24)
dpll_20071023\work\_opt\vopt39gvyk (380, 2007-10-24)
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