at7_ex17

所属分类VHDL/FPGA/Verilog
开发工具:Verilog
文件大小:48327KB
下载次数:0
上传日期:2020-01-14 16:39:36
上 传 者ming999
说明:  This example instantiates the DDR3 controller IP core module provided in Xilinx Vivado to achieve basic DDR3 reader operation. The simulation of the DDR3 IP core is achieved through an example of a test script automatically generated by the IP core.

文件列表:[举报垃圾]
at7_ex17\at.ip_user_files\ip\dist_mem_gen_0\dist_mem_gen_0.veo, 3053 , 2016-10-11
at7_ex17\at.ip_user_files\ip\dist_mem_gen_0\dist_mem_gen_0.vho, 3308 , 2016-10-11
at7_ex17\at.ip_user_files\ip\dist_mem_gen_0\dist_mem_gen_0_stub.v, 1328 , 2016-10-11
at7_ex17\at.ip_user_files\ip\dist_mem_gen_0\dist_mem_gen_0_stub.vhdl, 1447 , 2016-10-11
at7_ex17\at.ip_user_files\ip\ila_0\ila_0.veo, 3422 , 2016-10-11
at7_ex17\at.ip_user_files\ip\ila_0\ila_0_stub.v, 1721 , 2016-10-11
at7_ex17\at.ip_user_files\ip\ila_0\ila_0_stub.vhdl, 1964 , 2016-10-11
at7_ex17\at.ip_user_files\ipstatic\dist_mem_gen_v8_0_10\simulation\dist_mem_gen_v8_0.v, 16441 , 2016-10-11
at7_ex17\at.ip_user_files\mem_init_files\mig_a.prj, 9285 , 2016-10-10
at7_ex17\at.ip_user_files\README.txt, 130 , 2016-10-10
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\activehdl\compile.do, 480 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\activehdl\dist_mem_gen_0.sh, 4372 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\activehdl\dist_mem_gen_0.udo, 0 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\activehdl\file_info.txt, 276 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\activehdl\glbl.v, 1470 , 2016-06-02
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\activehdl\README.txt, 2220 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\activehdl\simulate.do, 352 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\activehdl\wave.do, 32 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\ies\dist_mem_gen_0.sh, 5553 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\ies\file_info.txt, 276 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\ies\glbl.v, 1470 , 2016-06-02
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\ies\README.txt, 2220 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\ies\run.f, 297 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\modelsim\compile.do, 463 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\modelsim\dist_mem_gen_0.sh, 4676 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\modelsim\dist_mem_gen_0.udo, 0 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\modelsim\file_info.txt, 276 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\modelsim\glbl.v, 1470 , 2016-06-02
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\modelsim\README.txt, 2220 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\modelsim\simulate.do, 338 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\modelsim\wave.do, 32 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\questa\compile.do, 451 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\questa\dist_mem_gen_0.sh, 4793 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\questa\dist_mem_gen_0.udo, 0 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\questa\elaborate.do, 210 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\questa\file_info.txt, 276 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\questa\glbl.v, 1470 , 2016-06-02
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\questa\README.txt, 2220 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\questa\simulate.do, 205 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\questa\wave.do, 32 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\README.txt, 3236 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\riviera\compile.do, 470 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\riviera\dist_mem_gen_0.sh, 4371 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\riviera\dist_mem_gen_0.udo, 0 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\riviera\file_info.txt, 276 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\riviera\glbl.v, 1470 , 2016-06-02
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\riviera\README.txt, 2220 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\riviera\simulate.do, 352 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\riviera\wave.do, 32 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\vcs\dist_mem_gen_0.sh, 6711 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\vcs\file_info.txt, 276 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\vcs\glbl.v, 1470 , 2016-06-02
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\vcs\README.txt, 2220 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\vcs\simulate.do, 11 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\xsim\cmd.tcl, 464 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\xsim\dist_mem_gen_0.sh, 3964 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\xsim\elab.opt, 215 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\xsim\file_info.txt, 276 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\xsim\glbl.v, 1470 , 2016-06-02
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\xsim\README.txt, 2220 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\xsim\vlog.prj, 250 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\dist_mem_gen_0\xsim\xsim.ini, 92 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\activehdl\compile.do, 2220 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\activehdl\file_info.txt, 3857 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\activehdl\glbl.v, 1470 , 2016-06-02
at7_ex17\at.ip_user_files\sim_scripts\ila_0\activehdl\ila_0.sh, 4255 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\activehdl\ila_0.udo, 0 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\activehdl\README.txt, 2175 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\activehdl\simulate.do, 308 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\activehdl\wave.do, 32 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\ies\file_info.txt, 3857 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\ies\glbl.v, 1470 , 2016-06-02
at7_ex17\at.ip_user_files\sim_scripts\ila_0\ies\ila_0.sh, 5768 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\ies\README.txt, 2175 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\ies\run.f, 837 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\modelsim\compile.do, 2207 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\modelsim\file_info.txt, 3857 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\modelsim\glbl.v, 1470 , 2016-06-02
at7_ex17\at.ip_user_files\sim_scripts\ila_0\modelsim\ila_0.sh, 4559 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\modelsim\ila_0.udo, 0 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\modelsim\README.txt, 2175 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\modelsim\simulate.do, 303 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\modelsim\wave.do, 32 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\questa\compile.do, 2191 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\questa\elaborate.do, 175 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\questa\file_info.txt, 3857 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\questa\glbl.v, 1470 , 2016-06-02
at7_ex17\at.ip_user_files\sim_scripts\ila_0\questa\ila_0.sh, 4676 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\questa\ila_0.udo, 0 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\questa\README.txt, 2175 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\questa\simulate.do, 187 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\questa\wave.do, 32 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\README.txt, 3236 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\riviera\compile.do, 2210 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\riviera\file_info.txt, 3857 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\riviera\glbl.v, 1470 , 2016-06-02
at7_ex17\at.ip_user_files\sim_scripts\ila_0\riviera\ila_0.sh, 4254 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\riviera\ila_0.udo, 0 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\riviera\README.txt, 2175 , 2016-10-11
at7_ex17\at.ip_user_files\sim_scripts\ila_0\riviera\simulate.do, 308 , 2016-10-11

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