Modelsim_Source

所属分类VHDL/FPGA/Verilog
开发工具:Verilog
文件大小:2412KB
下载次数:0
上传日期:2020-04-14 11:31:55
上 传 者elen12
说明:  一些用Modelsim仿真的verilog源代码,包括计数器,移位寄存器等。
(Some Verilog source codes simulated by Modelsim include counter, shift register, etc.)

文件列表:[举报垃圾]
Source\Ch1\1-1\fulladd.v, 181 , 2009-08-15
Source\Ch1\1-1\test.v, 424 , 2009-06-04
Source\Ch1\1-2\fulladd.v, 181 , 2009-08-15
Source\Ch1\1-2\quick.cr.mti, 233 , 2009-06-04
Source\Ch1\1-2\quick.mpf, 25480 , 2009-06-04
Source\Ch1\1-2\test.v, 424 , 2009-06-04
Source\Ch3\3-1\ac.v, 251 , 2005-04-15
Source\Ch3\3-1\alu.v, 380 , 2005-04-15
Source\Ch3\3-1\ar.v, 204 , 2005-04-15
Source\Ch3\3-1\control.v, 2843 , 2005-04-15
Source\Ch3\3-1\cpu.v, 873 , 2009-08-16
Source\Ch3\3-1\dr.v, 219 , 2005-04-15
Source\Ch3\3-1\ir.v, 202 , 2005-04-15
Source\Ch3\3-1\m.v, 357 , 2009-08-16
Source\Ch3\3-1\pc.v, 231 , 2005-04-15
Source\Ch3\3-1\top.v, 245 , 2009-08-16
Source\Ch3\3-2\module_lib\counter.v, 1288 , 2012-07-28
Source\Ch3\3-2\testbench\tcounter.v, 624 , 2012-07-28
Source\Ch4\4-1\freedes.vhd, 62971 , 2009-08-16
Source\Ch4\4-1\testbench.vhd, 7803 , 2018-11-26
Source\Ch4\4-1\testbench.vhd.bak, 7556 , 2009-08-16
Source\Ch4\4-2\assemble.v, 1877 , 2009-08-16
Source\Ch4\4-2\constants.v, 2202 , 2009-08-16
Source\Ch4\4-2\exponent.v, 996 , 2009-08-16
Source\Ch4\4-2\flag.v, 959 , 2009-08-16
Source\Ch4\4-2\fpmul.v, 4618 , 2009-08-16
Source\Ch4\4-2\multiply.v, 642 , 2009-08-16
Source\Ch4\4-2\normalize.v, 1061 , 2009-08-16
Source\Ch4\4-2\prenorm.v, 2419 , 2008-04-11
Source\Ch4\4-2\preprocess.v, 2421 , 2009-08-16
Source\Ch4\4-2\round.v, 4792 , 2009-08-16
Source\Ch4\4-2\shift.v, 2499 , 2009-08-16
Source\Ch4\4-2\special.v, 2303 , 2009-08-16
Source\Ch4\4-2\SynTestbed.v, 1380 , 2009-07-14
Source\Ch4\4-3\control.v, 2010 , 2012-07-28
Source\Ch4\4-3\retrieve.v, 1183 , 2012-07-28
Source\Ch4\4-3\ringbuf.v, 1581 , 2012-07-28
Source\Ch4\4-3\run.do, 893 , 2012-07-28
Source\Ch4\4-3\store.v, 1280 , 2012-07-28
Source\Ch4\4-3\test_ringbuf.cpp, 351 , 2012-07-28
Source\Ch4\4-3\test_ringbuf.h, 4590 , 2012-07-28
Source\Ch5\5-1\and2.v, 818 , 2012-07-28
Source\Ch5\5-1\cache.v, 5108 , 2012-07-28
Source\Ch5\5-1\gates.v, 1348 , 2012-07-28
Source\Ch5\5-1\memory.v, 1099 , 2012-07-28
Source\Ch5\5-1\proc.v, 2764 , 2012-07-28
Source\Ch5\5-1\set.v, 1845 , 2012-07-28
Source\Ch5\5-1\top.v, 967 , 2012-07-28
Source\Ch5\5-2\divclk3.v, 838 , 2009-08-16
Source\Ch5\5-2\tb_divclk3.v, 410 , 2009-08-16
Source\Ch5\5-3\fifo_syn_flag.v, 1560 , 2009-07-31
Source\Ch5\5-3\fifo_syn_ram.v, 1179 , 2009-07-31
Source\Ch5\5-3\fifo_syn_rdaddr_gen.v, 841 , 2009-08-01
Source\Ch5\5-3\fifo_syn_top.v, 1364 , 2009-07-31
Source\Ch5\5-3\fifo_syn_wraddr_gen.v, 846 , 2009-07-31
Source\Ch5\5-3\fifo_top_tb.v, 1192 , 2009-07-31
Source\Ch5\5-4\div2.v, 3511 , 2007-12-11
Source\Ch5\5-4\my_design_out.wlf, 40960 , 2009-08-01
Source\Ch5\5-4\tb_div2.v, 3061 , 2013-01-25
Source\Ch5\5-4\wave_test.v, 518 , 2013-01-24
Source\Ch6\6-1\counter.fsdb, 4730 , 2013-01-25
Source\Ch6\6-1\counter.v, 788 , 2009-08-12
Source\Ch6\6-1\novas.vhd, 8442 , 2005-05-04
Source\Ch6\6-1\tb_counter.v, 389 , 2013-01-25
Source\Ch6\6-2\modsimrand.v, 1533 , 2011-11-08
Source\Ch6\6-2\modsimrand.vhd, 850 , 2013-01-28
Source\Ch6\6-2\modsimrand_plot.m, 3413 , 2013-01-28
Source\Ch6\6-3\inverter.vhd, 426 , 2013-01-28
Source\Ch6\6-3\mywork.slx, 12565 , 2013-01-28
Source\Ch6\6-4\rcosflt_rtl.v, 34432 , 2010-05-10
Source\Ch6\6-4\rcosflt_tb.mdl, 26199 , 2010-05-10
Source\Ch7\7-1\constants.v, 965 , 2008-05-21
Source\Ch7\7-1\final_out.v, 4456 , 2009-08-16
Source\Ch7\7-1\fpadd.v, 3449 , 2009-08-16
Source\Ch7\7-1\fpalign.v, 2238 , 2009-08-16
Source\Ch7\7-1\mantadd.v, 1388 , 2009-08-16
Source\Ch7\7-1\normlizeadd.v, 2995 , 2009-08-16
Source\Ch7\7-1\rounderadd.v, 1986 , 2009-08-16
Source\Ch7\7-1\specialadd.v, 1236 , 2009-08-16
Source\Ch7\7-1\tb_fpadd.v, 358 , 2009-08-17
Source\Ch7\7-2\altera_primitives.v, 35058 , 2012-11-08
Source\Ch7\7-2\cycloneiii_atoms.v, 261023 , 2012-11-08
Source\Ch7\7-2\fpadd.vo, 565084 , 2013-01-29
Source\Ch7\7-2\fpadd_v.sdo, 433685 , 2013-01-29
Source\Ch7\7-2\tb_fpadd.v, 330 , 2009-08-13
Source\Ch7\7-3\fulladd.v, 181 , 2009-08-15
Source\Ch7\7-3\fulladd_timesim.sdf, 8035 , 2013-01-29
Source\Ch7\7-3\fulladd_timesim.v, 10042 , 2013-01-29
Source\Ch7\7-3\tb_fulladd.v, 358 , 2009-08-15
Source\Ch7\7-4\fulladd.v, 181 , 2009-08-15
Source\Ch7\7-4\modelsim副本.ini, 98775 , 2013-01-31
Source\Ch7\7-4\tb_fulladd.v, 358 , 2009-08-15
Source\Ch7\7-5\cla16.v, 1069 , 2013-02-01
Source\Ch7\7-5\claslice.v, 328 , 2013-02-01
Source\Ch7\7-5\ovi_xp\@a@g@e@b2\_primary.dat, 543 , 2013-02-01
Source\Ch7\7-5\ovi_xp\@a@g@e@b2\_primary.dbs, 605 , 2013-02-01
Source\Ch7\7-5\ovi_xp\@a@g@e@b2\_primary.vhd, 344 , 2013-02-01
Source\Ch7\7-5\ovi_xp\@a@l@e@b2\_primary.dat, 543 , 2013-02-01
Source\Ch7\7-5\ovi_xp\@a@l@e@b2\_primary.dbs, 605 , 2013-02-01
Source\Ch7\7-5\ovi_xp\@a@l@e@b2\_primary.vhd, 344 , 2013-02-01

近期下载者

相关文件

评论我要评论

收藏者