FIFO

所属分类VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:252KB
下载次数:0
上传日期:2020-04-14 22:13:01
上 传 者hayto
说明:  包含同步异步FIFO的veilog代码描述,包含注释适合学习
(A description of the veilog code containing synchronous and asynchronous FIFO, with comments suitable for learning)

文件列表:[举报垃圾]
afifo_design, 0 , 2010-07-24
afifo_design\sim, 0 , 2010-08-18
afifo_design\sim\do.do, 302 , 2010-03-17
afifo_design\sim\transcript, 1296 , 2010-08-18
afifo_design\sim\vsim.wlf, 32768 , 2010-03-17
afifo_design\sim\work, 0 , 2010-07-24
afifo_design\sim\work\@afifo, 0 , 2010-07-24
afifo_design\sim\work\@afifo\_primary.dat, 1796 , 2010-03-17
afifo_design\sim\work\@afifo\_primary.dbs, 5442 , 2010-03-17
afifo_design\sim\work\@afifo\_primary.vhd, 716 , 2010-03-17
afifo_design\sim\work\@afifo\verilog.asm, 14992 , 2010-03-17
afifo_design\sim\work\@afifo\verilog.rw, 3857 , 2010-03-17
afifo_design\sim\work\@afifo_mem, 0 , 2010-07-24
afifo_design\sim\work\@afifo_mem\_primary.dat, 1570 , 2010-03-17
afifo_design\sim\work\@afifo_mem\_primary.dbs, 3987 , 2010-03-17
afifo_design\sim\work\@afifo_mem\_primary.vhd, 652 , 2010-03-17
afifo_design\sim\work\@afifo_mem\verilog.asm, 21576 , 2010-03-17
afifo_design\sim\work\@afifo_mem\verilog.rw, 4470 , 2010-03-17
afifo_design\sim\work\@afifo_rptr_empty, 0 , 2010-07-24
afifo_design\sim\work\@afifo_rptr_empty\_primary.dat, 752 , 2010-03-17
afifo_design\sim\work\@afifo_rptr_empty\_primary.dbs, 2278 , 2010-03-17
afifo_design\sim\work\@afifo_rptr_empty\_primary.vhd, 480 , 2010-03-17
afifo_design\sim\work\@afifo_rptr_empty\verilog.asm, 13344 , 2010-03-17
afifo_design\sim\work\@afifo_rptr_empty\verilog.rw, 2531 , 2010-03-17
afifo_design\sim\work\@afifo_sync_r2w, 0 , 2010-07-24
afifo_design\sim\work\@afifo_sync_r2w\_primary.dat, 869 , 2010-03-17
afifo_design\sim\work\@afifo_sync_r2w\_primary.dbs, 2278 , 2010-03-17
afifo_design\sim\work\@afifo_sync_r2w\_primary.vhd, 476 , 2010-03-17
afifo_design\sim\work\@afifo_sync_r2w\verilog.asm, 9120 , 2010-03-17
afifo_design\sim\work\@afifo_sync_r2w\verilog.rw, 2590 , 2010-03-17
afifo_design\sim\work\@afifo_sync_w2r, 0 , 2010-07-24
afifo_design\sim\work\@afifo_sync_w2r\_primary.dat, 869 , 2010-03-17
afifo_design\sim\work\@afifo_sync_w2r\_primary.dbs, 2278 , 2010-03-17
afifo_design\sim\work\@afifo_sync_w2r\_primary.vhd, 476 , 2010-03-17
afifo_design\sim\work\@afifo_sync_w2r\verilog.asm, 9128 , 2010-03-17
afifo_design\sim\work\@afifo_sync_w2r\verilog.rw, 2598 , 2010-03-17
afifo_design\sim\work\@afifo_wptr_full, 0 , 2010-07-24
afifo_design\sim\work\@afifo_wptr_full\_primary.dat, 749 , 2010-03-17
afifo_design\sim\work\@afifo_wptr_full\_primary.dbs, 2240 , 2010-03-17
afifo_design\sim\work\@afifo_wptr_full\_primary.vhd, 478 , 2010-03-17
afifo_design\sim\work\@afifo_wptr_full\verilog.asm, 13328 , 2010-03-17
afifo_design\sim\work\@afifo_wptr_full\verilog.rw, 2515 , 2010-03-17
afifo_design\sim\work\_info, 1360 , 2010-03-17
afifo_design\sim\work\_temp, 0 , 2010-07-24
afifo_design\sim\work\_vmake, 26 , 2010-03-17
afifo_design\sim\work\tb, 0 , 2010-07-24
afifo_design\sim\work\tb\_primary.dat, 1240 , 2010-03-17
afifo_design\sim\work\tb\_primary.dbs, 3125 , 2010-03-17
afifo_design\sim\work\tb\_primary.vhd, 64 , 2010-03-17
afifo_design\sim\work\tb\verilog.asm, 11152 , 2010-03-17
afifo_design\sim\work\tb\verilog.rw, 4173 , 2010-03-17
afifo_design\src, 0 , 2010-07-24
afifo_design\src\Afifo.v, 5805 , 2010-04-09
afifo_design\src\Afifo_mem.v, 5600 , 2010-04-09
afifo_design\src\Afifo_rptr_empty.v, 5434 , 2010-04-09
afifo_design\src\Afifo_sync_r2w.v, 5301 , 2010-04-09
afifo_design\src\Afifo_sync_w2r.v, 5340 , 2010-04-09
afifo_design\src\Afifo_wptr_full.v, 5351 , 2010-04-09
afifo_design\tb, 0 , 2010-07-24
afifo_design\tb\tb.v, 1745 , 2010-03-17
asyn_fifo, 0 , 2020-04-01
asyn_fifo\asyn_fifo.v, 2937 , 2019-06-30
asyn_fifo\asyn_fifo_tb.sv, 1111 , 2019-06-30
asyn_fifo\bin_to_gray.v, 387 , 2019-06-30
asyn_fifo\RAM.v, 806 , 2018-07-26
asyn_fifo\read_part.v, 1805 , 2020-03-03
asyn_fifo\syn.v, 490 , 2019-06-30
asyn_fifo\write_part.v, 922 , 2020-03-03
asyn_fifo_v2, 0 , 2020-04-01
asyn_fifo_v2\.read_part.v.un~, 8802 , 2019-06-30
asyn_fifo_v2\.write_part.v.un~, 8803 , 2019-06-30
asyn_fifo_v2\ASYN_FIFO.cr.mti, 2643 , 2019-04-16
asyn_fifo_v2\ASYN_FIFO.mpf, 97072 , 2019-04-14
asyn_fifo_v2\asyn_fifo.v, 2937 , 2019-06-30
asyn_fifo_v2\asyn_fifo.v~, 2936 , 2018-12-02
asyn_fifo_v2\ASYN_FIFO, 0 , 2020-04-01
asyn_fifo_v2\ASYN_FIFO\_info, 4638 , 2019-04-14
asyn_fifo_v2\ASYN_FIFO\_lib.qdb, 49152 , 2019-04-14
asyn_fifo_v2\ASYN_FIFO\_lib1_0.qdb, 32768 , 2019-04-14
asyn_fifo_v2\ASYN_FIFO\_lib1_0.qpg, 131072 , 2019-04-14
asyn_fifo_v2\ASYN_FIFO\_lib1_0.qtl, 49637 , 2019-04-14
asyn_fifo_v2\ASYN_FIFO\_vmake, 29 , 2019-04-14
asyn_fifo_v2\asyn_fifo_tb.sv, 1111 , 2019-06-30
asyn_fifo_v2\asyn_fifo_tb.sv~, 1109 , 2018-07-26
asyn_fifo_v2\bin_to_gray.v, 387 , 2019-06-30
asyn_fifo_v2\bin_to_gray.v~, 385 , 2018-07-26
asyn_fifo_v2\RAM.v, 806 , 2018-07-26
asyn_fifo_v2\read_part.v, 1805 , 2020-03-03
asyn_fifo_v2\read_part.v~, 1805 , 2019-06-30
asyn_fifo_v2\syn.v, 490 , 2019-06-30
asyn_fifo_v2\syn.v~, 490 , 2018-07-26
asyn_fifo_v2\vsim.wlf, 73728 , 2019-04-14
asyn_fifo_v2\write_part.v, 922 , 2020-03-03
asyn_fifo_v2\write_part.v~, 922 , 2019-06-30
eetop.cn_afifo_design.rar, 60353 , 2020-04-07
FIFO_Channel.v, 4278 , 2020-03-29
FIFO_Dual_Part.v, 5396 , 2020-04-01
FIFO_Dual_Part, 0 , 2020-04-01
FIFO_Dual_Part\FIFO.cr.mti, 792 , 2020-04-01
FIFO_Dual_Part\FIFO.mpf, 98330 , 2020-04-01

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