lab5

所属分类VHDL/FPGA/Verilog
开发工具:Verilog
文件大小:849KB
下载次数:0
上传日期:2020-04-15 18:06:07
上 传 者肖想
说明:  用Verilog语言来编写的32位spi,使用robei工具。
(32-bit SPI written in Verilog)

文件列表:[举报垃圾]
lab5\spi\project_1\project_1.cache\wt\gui_handlers.wdf, 3858 , 2020-04-06
lab5\spi\project_1\project_1.cache\wt\java_command_handlers.wdf, 618 , 2020-04-06
lab5\spi\project_1\project_1.cache\wt\project.wpc, 121 , 2020-04-06
lab5\spi\project_1\project_1.cache\wt\synthesis.wdf, 5387 , 2020-04-06
lab5\spi\project_1\project_1.cache\wt\synthesis_details.wdf, 100 , 2020-04-06
lab5\spi\project_1\project_1.cache\wt\webtalk_pa.xml, 4034 , 2020-04-06
lab5\spi\project_1\project_1.hw\project_1.lpr, 290 , 2020-04-06
lab5\spi\project_1\project_1.runs\.jobs\vrs_config_1.xml, 227 , 2020-04-06
lab5\spi\project_1\project_1.runs\.jobs\vrs_config_2.xml, 241 , 2020-04-06
lab5\spi\project_1\project_1.runs\.jobs\vrs_config_3.xml, 241 , 2020-04-06
lab5\spi\project_1\project_1.runs\.jobs\vrs_config_4.xml, 248 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.init_design.begin.rst, 183 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.init_design.end.rst, 0 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.opt_design.begin.rst, 183 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.opt_design.end.rst, 0 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.place_design.begin.rst, 183 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.place_design.end.rst, 0 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.route_design.begin.rst, 183 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.route_design.end.rst, 0 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.vivado.begin.rst, 364 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.vivado.end.rst, 0 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.Vivado_Implementation.queue.rst, 0 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.write_bitstream.begin.rst, 182 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\.write_bitstream.end.rst, 0 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\gen_run.xml, 6207 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\htr.txt, 399 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\init_design.pb, 2044 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\ISEWrap.js, 7308 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\ISEWrap.sh, 1623 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\opt_design.pb, 9043 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\place_design.pb, 12834 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\project.wdf, 3634 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\route_design.pb, 13268 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\rundef.js, 1396 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\runme.bat, 229 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\runme.log, 27221 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\runme.sh, 1269 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim.bit, 4045667 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim.tcl, 2201 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim.vdi, 27443 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_114956.backup.vdi, 23598 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_bus_skew_routed.pb, 30 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_bus_skew_routed.rpt, 869 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_bus_skew_routed.rpx, 1023 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_clock_utilization_routed.rpt, 10611 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_control_sets_placed.rpt, 2877 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_drc_opted.pb, 37 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_drc_opted.rpt, 2614 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_drc_opted.rpx, 2804 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_drc_routed.pb, 37 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_drc_routed.rpt, 2657 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_drc_routed.rpx, 2936 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_io_placed.rpt, 119601 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_methodology_drc_routed.pb, 52 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_methodology_drc_routed.rpt, 3532 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_methodology_drc_routed.rpx, 3451 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_opt.dcp, 212683 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_placed.dcp, 219671 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_power_routed.rpt, 8268 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_power_routed.rpx, 13585 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_power_summary_routed.pb, 722 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_routed.dcp, 224546 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_route_status.pb, 43 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_route_status.rpt, 588 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_timing_summary_routed.pb, 52 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_timing_summary_routed.rpt, 7447 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_timing_summary_routed.rpx, 5553 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_utilization_placed.pb, 224 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\spi_sim_utilization_placed.rpt, 8394 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\usage_statistics_webtalk.html, 21499 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\usage_statistics_webtalk.xml, 29435 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\vivado.jou, 740 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\vivado.pb, 149 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\vivado_114956.backup.jou, 741 , 2020-04-06
lab5\spi\project_1\project_1.runs\impl_1\write_bitstream.pb, 5634 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\.vivado.begin.rst, 181 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\.vivado.end.rst, 0 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\.Vivado_Synthesis.queue.rst, 0 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\.Xil\spi_sim_propImpl.xdc, 2019 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\gen_run.xml, 1822 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\htr.txt, 391 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\ISEWrap.js, 7308 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\ISEWrap.sh, 1623 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\project.wdf, 3634 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\rundef.js, 1321 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\runme.bat, 229 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\runme.log, 17674 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\runme.sh, 1202 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\spi_sim.dcp, 9684 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\spi_sim.tcl, 2538 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\spi_sim.vds, 17767 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\spi_sim_utilization_synth.pb, 224 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\spi_sim_utilization_synth.rpt, 6732 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\vivado.jou, 736 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\vivado.pb, 28151 , 2020-04-06
lab5\spi\project_1\project_1.runs\synth_1\__synthesis_is_complete__, 0 , 2020-04-06
lab5\spi\project_1\project_1.srcs\constrs_1\new\spi_constrain.xdc, 1230 , 2020-04-06
lab5\spi\project_1\project_1.xpr, 7147 , 2020-04-06
lab5\spi_master.model, 3446 , 2020-04-06
lab5\spi_master.vvp, 7710 , 2020-04-06

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