aes_core
所属分类：加密解密
开发工具：Others
文件大小：78KB
下载次数：173
上传日期：2008-02-15 14:35:02
上 传 者：
yuansc
说明： Verilog实现AES加密算法
密码模块作为安全保密系统的重要组成部分，其核心任务就是加密数据。分组密码算法AES以其高效率、低开销、实现简单等特点目前被广泛应用于密码模块的研制中。密码模块一般被设计成外接在主机串口或并口的一个硬件设备或是一块插卡，具有速度快，低时延的特点。而从整体发展趋势来看，嵌入式密码模块由于灵活，适用于多种用户终端、通信设备和武器平台，将会得到更加广泛的应用
(AES encryption algorithm realize Verilog module password security system as an important part of its core mission is to encrypt the data. AES block cipher algorithm for its high efficiency, low overhead, simple features such as the current password is widely used in research and development modules. Password modules are generally designed to host external serial or parallel port of a hardware device or a card with a high speed, low latency characteristics. From the overall development trend, the embedded code module as a result of flexible and applicable to many user terminals, communications equipment and weapons platforms, will be more widely applied)
文件列表:
aes_core\bench\CVS\Entries (14, 2007-10-06)
aes_core\bench\CVS\Repository (15, 2007-10-06)
aes_core\bench\CVS\Root (13, 2007-10-06)
aes_core\bench\verilog\CVS\Entries (51, 2007-10-06)
aes_core\bench\verilog\CVS\Repository (23, 2007-10-06)
aes_core\bench\verilog\CVS\Root (13, 2007-10-06)
aes_core\bench\verilog\test_bench_top.v (37033, 2002-11-13)
aes_core\CVS\Entries (104, 2007-10-06)
aes_core\CVS\Repository (9, 2007-10-06)
aes_core\CVS\Root (13, 2007-10-06)
aes_core\doc\aes.pdf (73346, 2002-11-13)
aes_core\doc\CVS\Entries (45, 2007-10-06)
aes_core\doc\CVS\Repository (13, 2007-10-06)
aes_core\doc\CVS\Root (13, 2007-10-06)
aes_core\rtl\CVS\Entries (14, 2007-10-06)
aes_core\rtl\CVS\Repository (13, 2007-10-06)
aes_core\rtl\CVS\Root (13, 2007-10-06)
aes_core\rtl\verilog\aes_cipher_top.v (10230, 2002-11-09)
aes_core\rtl\verilog\aes_inv_cipher_top.v (11671, 2002-11-09)
aes_core\rtl\verilog\aes_inv_sbox.v (8257, 2002-11-09)
aes_core\rtl\verilog\aes_key_expand_128.v (3914, 2002-11-09)
aes_core\rtl\verilog\aes_rcon.v (3773, 2002-11-09)
aes_core\rtl\verilog\aes_sbox.v (8246, 2002-11-09)
aes_core\rtl\verilog\CVS\Entries (358, 2007-10-06)
aes_core\rtl\verilog\CVS\Repository (21, 2007-10-06)
aes_core\rtl\verilog\CVS\Root (13, 2007-10-06)
aes_core\rtl\verilog\timescale.v (22, 2002-11-13)
aes_core\sim\CVS\Entries (14, 2007-10-06)
aes_core\sim\CVS\Repository (13, 2007-10-06)
aes_core\sim\CVS\Root (13, 2007-10-06)
aes_core\sim\rtl_sim\bin\CVS\Entries (47, 2007-10-06)
aes_core\sim\rtl_sim\bin\CVS\Repository (25, 2007-10-06)
aes_core\sim\rtl_sim\bin\CVS\Root (13, 2007-10-06)
aes_core\sim\rtl_sim\bin\Makefile (2236, 2002-11-09)
aes_core\sim\rtl_sim\CVS\Entries (20, 2007-10-06)
aes_core\sim\rtl_sim\CVS\Repository (21, 2007-10-06)
aes_core\sim\rtl_sim\CVS\Root (13, 2007-10-06)
aes_core\sim\rtl_sim\run\CVS\Entries (12, 2007-10-06)
aes_core\sim\rtl_sim\run\CVS\Repository (25, 2007-10-06)
aes_core\sim\rtl_sim\run\CVS\Root (13, 2007-10-06)
... ...
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