dividers.tar
所属分类：VHDL/FPGA/Verilog
开发工具：TEXT
文件大小：5KB
下载次数：34
上传日期：2008-02-28 15:42:17
上 传 者：
想好再说
说明： 无符号类型的除法器,有VHDL语言描述了无符号的除法器,包括测试文件
(Unsigned type of divider, a VHDL language description of the divider unsigned, including the test file)
文件列表:
dividers (0, 2007-09-12)
dividers\CVS (0, 2007-09-12)
dividers\CVS\Root (13, 2007-09-12)
dividers\CVS\Repository (9, 2007-09-12)
dividers\CVS\Entries (22, 2007-09-12)
dividers\bench (0, 2007-09-12)
dividers\bench\CVS (0, 2007-09-12)
dividers\bench\CVS\Root (13, 2007-09-12)
dividers\bench\CVS\Repository (15, 2007-09-12)
dividers\bench\CVS\Entries (14, 2007-09-12)
dividers\bench\verilog (0, 2007-09-12)
dividers\bench\verilog\CVS (0, 2007-09-12)
dividers\bench\verilog\CVS\Root (13, 2007-09-12)
dividers\bench\verilog\CVS\Repository (23, 2007-09-12)
dividers\bench\verilog\CVS\Entries (94, 2007-09-12)
dividers\bench\verilog\bench_div_top.v (5578, 2003-09-17)
dividers\bench\verilog\timescale.v (23, 2002-10-31)
dividers\rtl (0, 2007-09-12)
dividers\rtl\CVS (0, 2007-09-12)
dividers\rtl\CVS\Root (13, 2007-09-12)
dividers\rtl\CVS\Repository (13, 2007-09-12)
dividers\rtl\CVS\Entries (14, 2007-09-12)
dividers\rtl\verilog (0, 2007-09-12)
dividers\rtl\verilog\CVS (0, 2007-09-12)
dividers\rtl\verilog\CVS\Root (13, 2007-09-12)
dividers\rtl\verilog\CVS\Repository (21, 2007-09-12)
dividers\rtl\verilog\CVS\Entries (171, 2007-09-12)
dividers\rtl\verilog\div.v (5068, 2002-10-30)
dividers\rtl\verilog\div_su.v (4577, 2002-10-31)
dividers\rtl\verilog\div_us.v (3461, 2002-10-30)
dividers\rtl\verilog\div_uu.v (5892, 2003-09-17)
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