ethernet_tri_mode_rtl.tar
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：38KB
下载次数：67
上传日期：2008-04-05 15:35:38
上 传 者：
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说明： verilog实现的异步UART代码，包括发送模块、接收模块，波特率可配置，另附PC机的c代码
(Verilog realize asynchronous UART code, including the transmission module, receiver module, the baud rate can be configured, an additional PC-c code)
文件列表:
ethernet_tri_mode\rtl (0, 2007-12-25)
ethernet_tri_mode\rtl\verilog (0, 2007-12-25)
ethernet_tri_mode\rtl\verilog\eth_miim.v (16642, 2006-01-19)
ethernet_tri_mode\rtl\verilog\MAC_rx (0, 2007-12-25)
ethernet_tri_mode\rtl\verilog\MAC_rx\MAC_rx_ctrl.v (22362, 2006-06-25)
ethernet_tri_mode\rtl\verilog\MAC_rx\MAC_rx_FF.v (24845, 2006-06-25)
ethernet_tri_mode\rtl\verilog\MAC_rx\MAC_rx_add_chk.v (6819, 2006-01-19)
ethernet_tri_mode\rtl\verilog\MAC_rx\Broadcast_filter.v (5222, 2006-01-19)
ethernet_tri_mode\rtl\verilog\MAC_rx\CRC_chk.v (6281, 2006-01-19)
ethernet_tri_mode\rtl\verilog\MAC_rx\CVS (0, 2007-12-25)
ethernet_tri_mode\rtl\verilog\MAC_rx\CVS\Repository (37, 2007-12-25)
ethernet_tri_mode\rtl\verilog\MAC_rx\CVS\Entries (234, 2007-12-25)
ethernet_tri_mode\rtl\verilog\MAC_rx\CVS\Root (13, 2007-12-25)
ethernet_tri_mode\rtl\verilog\miim (0, 2007-12-25)
ethernet_tri_mode\rtl\verilog\miim\eth_clockgen.v (5675, 2005-12-13)
ethernet_tri_mode\rtl\verilog\miim\eth_shiftreg.v (6915, 2005-12-13)
ethernet_tri_mode\rtl\verilog\miim\CVS (0, 2007-12-25)
ethernet_tri_mode\rtl\verilog\miim\CVS\Repository (35, 2007-12-25)
ethernet_tri_mode\rtl\verilog\miim\CVS\Entries (192, 2007-12-25)
ethernet_tri_mode\rtl\verilog\miim\CVS\Root (13, 2007-12-25)
ethernet_tri_mode\rtl\verilog\miim\eth_outputcontrol.v (6489, 2005-12-13)
ethernet_tri_mode\rtl\verilog\miim\timescale.v (3222, 2005-12-13)
ethernet_tri_mode\rtl\verilog\reg_int.v (10283, 2006-11-18)
ethernet_tri_mode\rtl\verilog\RMON (0, 2007-12-25)
ethernet_tri_mode\rtl\verilog\RMON\RMON_dpram.v (1292, 2006-01-19)
ethernet_tri_mode\rtl\verilog\RMON\RMON_ctrl.v (10153, 2006-06-25)
ethernet_tri_mode\rtl\verilog\RMON\RMON_addr_gen.v (11414, 2006-06-25)
ethernet_tri_mode\rtl\verilog\RMON\CVS (0, 2007-12-25)
ethernet_tri_mode\rtl\verilog\RMON\CVS\Repository (35, 2007-12-25)
ethernet_tri_mode\rtl\verilog\RMON\CVS\Entries (139, 2007-12-25)
ethernet_tri_mode\rtl\verilog\RMON\CVS\Root (13, 2007-12-25)
ethernet_tri_mode\rtl\verilog\header.v (190, 2006-01-19)
ethernet_tri_mode\rtl\verilog\Phy_int.v (8582, 2006-01-19)
ethernet_tri_mode\rtl\verilog\MAC_top.v (20637, 2006-01-19)
ethernet_tri_mode\rtl\verilog\MAC_rx.v (12177, 2006-11-18)
ethernet_tri_mode\rtl\verilog\MAC_tx (0, 2007-12-25)
ethernet_tri_mode\rtl\verilog\MAC_tx\CRC_gen.v (7343, 2006-01-19)
ethernet_tri_mode\rtl\verilog\MAC_tx\MAC_tx_FF.v (26498, 2006-06-25)
ethernet_tri_mode\rtl\verilog\MAC_tx\MAC_tx_addr_add.v (5937, 2006-01-19)
ethernet_tri_mode\rtl\verilog\MAC_tx\Ramdon_gen.v (5609, 2006-01-19)
... ...
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