文件列表:

Nios构成\standard.bdf (52672, 2006-11-27)
Nios构成\standard.pin (78063, 2006-11-27)
Nios构成\standard.qpf (1534, 2006-11-27)
Nios构成\add_constraints_for_ddr_sdram.tcl (76068, 2006-11-27)
Nios构成\altpllpll.cmp (935, 2006-11-27)
Nios构成\altpllpll.ppf (488, 2006-11-27)
Nios构成\altpllpll.vhd (17091, 2006-11-27)
Nios构成\auto_add_ddr_constraints.tcl (363, 2006-11-27)
Nios构成\auto_verify_ddr_timing.tcl (245, 2006-11-27)
Nios构成\button_pio.vhd (6323, 2006-11-27)
Nios构成\clock_0.vhd (38782, 2006-11-27)
Nios构成\constraints_out.txt (2529, 2006-11-27)
Nios构成\cpu.ocp (840, 2006-11-27)
Nios构成\cpu.vhd (643184, 2006-11-27)
Nios构成\cpu_ic_tag_ram.mif (1743, 2006-11-27)
Nios构成\cpu_jtag_debug_module.vhd (13161, 2006-11-27)
Nios构成\cpu_jtag_debug_module_wrapper.vhd (16696, 2006-11-27)
Nios构成\cpu_mult_cell.vhd (6470, 2006-11-27)
Nios构成\cpu_ociram_default_contents.mif (5878, 2006-11-27)
Nios构成\cpu_rf_ram_a.mif (558, 2006-11-27)
Nios构成\cpu_rf_ram_b.mif (558, 2006-11-27)
Nios构成\cpu_test_bench.vhd (90673, 2006-11-27)
Nios构成\ddr_lib_path.tcl (225, 2006-11-27)
Nios构成\ddr_pll_cycloneii.vhd (1573, 2006-11-27)
Nios构成\ddr_sdram.cmp (2552, 2006-11-27)
Nios构成\ddr_sdram.html (5558, 2006-11-27)
Nios构成\ddr_sdram.ppf (12463, 2006-11-27)
Nios构成\ddr_sdram.vhd (8432, 2006-11-27)
Nios构成\ddr_sdram_auk_ddr_clk_gen.vhd (4520, 2006-11-27)
Nios构成\ddr_sdram_auk_ddr_datapath.vhd (7548, 2006-11-27)
Nios构成\ddr_sdram_auk_ddr_datapath_pack.vhd (1206, 2006-11-27)
Nios构成\ddr_sdram_auk_ddr_dqs_group.vhd (36097, 2006-11-27)
Nios构成\ddr_sdram_auk_ddr_sdram.vhd (18527, 2006-11-27)
Nios构成\ddr_sdram_ddr_settings.txt (3470, 2006-11-27)
Nios构成\ddr_sdram_estimated_data.dat (1283, 2006-11-27)
Nios构成\ddr_sdram_example_driver.vhd (26359, 2006-11-27)
Nios构成\ddr_sdram_extraction_data.txt (21292, 2006-11-27)
Nios构成\ddr_sdram_extraction_log2.txt (57707, 2006-11-27)
Nios构成\ddr_sdram_post_summary.txt (1622, 2006-11-27)
Nios构成\ddr_sdram_pre_compile_ddr_timing_summary.txt (117, 2006-11-27)
... ...

readme - Standard Design Overview: This design is provided for all Nios development boards and highlights many of the standard features of the Nios II processor. Contents of the System: - Nios II/s Core - JTAG Debug Module (Level 1) - DDR SDRAM Controller (32MB) - SSRAM Controller (2MB) - CFI Flash Memory Interface (16MB) - EPCS Controller (with bootloader) - JTAG UART - UART (RS-232) - Two Timers - Ethernet Interface - LED PIO - Seven Segment Display PIO - Push Button PIO - LCD Display Interface - System ID Peripheral Hardware Specs: - Fmax > 85MHz - Resource Usage < 4500 LEs - Onchip Memory Usage < 7KB - Two PLLs - Up to four 9-bit DSP elements Supported Software Examples: - Blank Project - Hello World - Board Diagnostic - Count Binary - Dhrystone - Hello Free-Standing - Hello LED - Hello MicroC/OS II - Hello World Small - Host File System - MicroC/OS-II Message Box - Memory Test - MicroC/OS-II Tutorial - Simple Sockets Server - Web Server - Zip File System Further Notes: - Due to the library paths that are coded into the Quartus settings for this project, if a user wishes to modify the hardware design they must first strip out any old paths from within the project settings file (qsf). An example of this is as below: set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:auto_verify_ddr_timing.tcl" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_tb_functions.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_functions.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_input_buf.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_timers.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_avalon_if.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_bank_details.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_controller.vhd" set_global_assignment -name VHDL_FILE "C:/MegaCore/ddr_ddr2_sdram-v3.2.0/lib/auk_ddr_init.vhd" set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram_auk_ddr_dqs_group.v" set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram_auk_ddr_clk_gen.v" set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram_auk_ddr_datapath.v" set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram_auk_ddr_sdram.v" set_global_assignment -name VERILOG_FILE "C:/niosII_cycloneII_2c35/full_featured/ddr_sdram.v" set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:auto_add_ddr_constraints.tcl" Once these have been removed regenerate the embedded system in SOPC Builder to recreate new paths for the DDR on the local machine. - DDR memory is the main memory of the system, however SSRAM has a faster access speed (when using the same clock frequencies).

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