divider
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：3KB
下载次数：297
上传日期：2008-04-19 20:12:02
上 传 者：
ljpaula
说明： 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）
(Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into))
文件列表:
divider\divider.v (649, 2007-12-20)
divider\div_ctl.v (1585, 2007-12-20)
divider\div_datapath.v (1991, 2007-12-20)
divider\div_tb.v (3007, 2007-12-20)
divider\read me.txt (88, 2008-04-19)
divider (0, 2008-04-19)
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