FIR_verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：614KB
下载次数：415
上传日期：2008-04-24 23:11:39
上 传 者：
yejianchao
说明： 基于verilog的FIR滤波器，有两种实现方法，分别给出仿真波形
(Verilog based on the FIR filter, there are two methods, respectively, the simulation waveform)
文件列表:
FIR1\FIR1.qpf (899, 2007-06-05)
FIR1\FIR1.qsf (1720, 2007-06-05)
FIR1\db\wed.zsf (68, 2007-06-05)
FIR1\db\FIR1.db_info (135, 2007-06-05)
FIR1\db\add_sub_t8i.tdf (3722, 2007-06-05)
FIR1\db\add_sub_r8i.tdf (3377, 2007-06-05)
FIR1\db\add_sub_3ph.tdf (4400, 2007-06-05)
FIR1\db\add_sub_voh.tdf (3716, 2007-06-05)
FIR1\db\add_sub_7li.tdf (3727, 2007-06-05)
FIR1\db\add_sub_5li.tdf (3382, 2007-06-05)
FIR1\db\FIR1.eco.cdb (140, 2007-06-05)
FIR1\db\FIR1.cbx.xml (6554, 2007-06-05)
FIR1\db\FIR1.fnsim.cdb (35680, 2007-06-05)
FIR1\db\FIR1.fnsim.hdb (102035, 2007-06-05)
FIR1\db\FIR1.sld_design_entry_dsc.sci (133, 2007-06-05)
FIR1\db\FIR1.sim.qmsg (3562, 2007-06-05)
FIR1\db\FIR1.sim_ori.vwf (8126, 2007-06-05)
FIR1\db\FIR1.sim.hdb (2375, 2007-06-05)
FIR1\db\FIR1.eds_overflow (2, 2007-06-05)
FIR1\db\FIR1.sld_design_entry.sci (133, 2007-06-05)
FIR1\db\FIR1.sim.rdb (95459, 2007-06-05)
FIR1\db\FIR1.hif (1194, 2007-06-05)
FIR1\db\FIR1.(1).cnf.cdb (5748, 2007-06-05)
FIR1\db\FIR1.(1).cnf.hdb (1676, 2007-06-05)
FIR1\db\FIR1.hier_info (50932, 2007-06-05)
FIR1\db\FIR1.psp (0, 2007-06-05)
FIR1\db\FIR1.dbp (0, 2007-06-05)
FIR1\db\FIR1.syn_hier_info (0, 2007-06-05)
FIR1\db\FIR1.map.qmsg (285187, 2007-06-05)
FIR1\db\FIR1.(0).cnf.cdb (4943, 2007-06-05)
FIR1\db\FIR1.(0).cnf.hdb (1482, 2007-06-05)
FIR1\db\FIR1.rtlv_sg.cdb (7892, 2007-06-05)
FIR1\db\FIR1.rtlv.hdb (10751, 2007-06-05)
FIR1\db\FIR1.rtlv_sg_swap.cdb (767, 2007-06-05)
FIR1\db\FIR1.pre_map.hdb (10822, 2007-06-05)
FIR1\db\FIR1.pre_map.cdb (20778, 2007-06-05)
FIR1\db\FIR1.map.logdb (4, 2007-06-05)
FIR1\db\FIR1.sgdiff.cdb (6545, 2007-06-05)
FIR1\db\FIR1.sgdiff.hdb (11345, 2007-06-05)
FIR1\db\FIR1.map.cdb (6627, 2007-06-05)
... ...
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