BFSK_VHDL_CODING
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：259KB
下载次数：52
上传日期：2008-04-27 22:30:33
上 传 者：
sunset_yeah
说明： 使用DDS技术，应用altera公司的芯片，以及杭州康芯公司的试验箱，实现BFSK信号的调制解调
(The use of DDS technology, applications altera chips, as well as the core company in Hangzhou, Culture and Sport chamber, the realization of BFSK signal modulation and demodulation)
文件列表:
fsk\ADDER10B.VHD (349, 2004-07-10)
fsk\ADDER32B.VHD (350, 2004-07-09)
fsk\adder7b.vhd (340, 2007-05-31)
fsk\cmp_state.ini (2, 2007-06-01)
fsk\dds.asm.rpt (8057, 2007-06-25)
fsk\dds.cdf (296, 2007-06-01)
fsk\dds.done (26, 2007-06-25)
fsk\dds.fit.eqn (21807, 2007-05-31)
fsk\dds.fit.rpt (96730, 2007-06-25)
fsk\dds.fit.smsg (411, 2007-06-25)
fsk\dds.fit.summary (414, 2007-06-25)
fsk\dds.flow.rpt (4068, 2007-06-25)
fsk\dds.map.eqn (18679, 2007-05-31)
fsk\dds.map.rpt (33331, 2007-06-25)
fsk\dds.map.summary (316, 2007-06-25)
fsk\dds.pin (30337, 2007-06-25)
fsk\dds.pof (524489, 2007-06-25)
fsk\dds.qpf (897, 2007-05-31)
fsk\dds.qsf (2801, 2007-06-01)
fsk\dds.qws (3667, 2007-06-25)
fsk\dds.sim.rpt (28539, 2007-06-25)
fsk\dds.sof (281523, 2007-06-25)
fsk\dds.tan.rpt (106785, 2007-06-25)
fsk\dds.tan.summary (1263, 2007-06-25)
fsk\DDS.VHD (2571, 2007-06-25)
fsk\dds.vwf (9748, 2007-06-01)
fsk\dds_assignment_defaults.qdf (27091, 2007-06-01)
fsk\fsk_decode.vhd (1078, 2007-05-31)
fsk\LUT10X10.MIF (15191, 2004-07-10)
fsk\ps7.vhd (671, 2007-05-31)
fsk\REG10B.VHD (441, 2004-07-10)
fsk\REG32B.VHD (382, 2007-05-31)
fsk\reg7b.vhd (432, 2007-05-31)
fsk\sin7.mif (1184, 2007-05-31)
fsk\SIN_ROM.VHD (5849, 2007-05-31)
fsk\db\altsyncram_0sj2.tdf (16589, 2007-05-31)
fsk\db\altsyncram_5mp.tdf (8409, 2007-05-31)
fsk\db\altsyncram_6v51.tdf (2785, 2007-05-31)
fsk\db\altsyncram_hq21.tdf (8591, 2007-06-01)
fsk\db\dds.(0).cnf.cdb (2268, 2007-06-25)
... ...
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