ise_book
所属分类：系统设计方案
开发工具：VHDL
文件大小：8092KB
下载次数：92
上传日期：2008-04-30 19:31:10
上 传 者：
随风流云
说明： Xilinx ISE9.x FPGA\CPLD设计指南 原书光盘上的源码 包含大量vhdl源码
(Xilinx ISE9.x FPGACPLD Design Guide CD-ROM on the original source book contains a large amount of VHDL source code)
文件列表:
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.bld (860, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.cmd_log (948, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.lso (6, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.ncd (18758, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.ngc (20661, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.ngd (31982, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.ngr (10751, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.pad (26546, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.par (5571, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.pcf (214, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.prj (53, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.stx (0, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.syr (16377, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.twr (4183, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.twx (23435, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.unroutes (148, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.xpi (46, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter.xst (1210, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_fpga_editor.log (595, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_guide.ncd (18758, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_map.map (3645, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_map.mrp (11169, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_map.ncd (14022, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_map.ngm (57672, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_pad.csv (26578, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_pad.txt (134885, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_prev_built.ngd (31982, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_summary.html (8063, 2006-12-06)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_summary.xml (408, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_usage.xml (1991, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_ver.ise (276108, 2006-12-06)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_ver.ise_ISE_Backup (276108, 2006-12-06)
ise_book\Example-1-1\prescale_counter_ver\prescale_counter_ver.ntrc_log (68, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\xst\dump.xst\prescale_counter.prj\ntrc.scr (1237, 2006-12-05)
ise_book\Example-1-1\prescale_counter_ver\xst\dump.xst\prescale_counter.prj\ngx\notopt (0, 2007-12-26)
ise_book\Example-1-1\prescale_counter_ver\xst\dump.xst\prescale_counter.prj\ngx\opt (0, 2007-12-26)
ise_book\Example-1-1\prescale_counter_ver\xst\dump.xst\prescale_counter.prj\ngx (0, 2007-12-26)
ise_book\Example-1-1\prescale_counter_ver\xst\dump.xst\prescale_counter.prj (0, 2007-12-26)
ise_book\Example-1-1\prescale_counter_ver\xst\dump.xst (0, 2007-12-26)
ise_book\Example-1-1\prescale_counter_ver\xst\work\hdllib.ref (102, 2006-12-05)
... ...
The following files were generated for 'cnt16' in directory
D:\ise_book\Example-2-2:
cnt16.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
cnt16.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
cnt16.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
cnt16.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
cnt16.sym:
Please see the core data sheet.
cnt16.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
cnt16.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
cnt16.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
cnt16_xmdf.tcl:
Please see the core data sheet.
cnt16_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
cnt16_readme.txt:
Text file indicating the files generated and how they are used.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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