test

所属分类:VHDL/FPGA/Verilog
开发工具:Others
文件大小:142KB
下载次数:109
上传日期:2008-05-08 01:41:05
上 传 者ysw1005
说明:  VHDL实现倍频--偶数倍 分频电路 --分频倍数=2(n+1)
(VHDL realize many times frequency multiplier circuit dual frequency multiplier = 2 (n+ 1))

文件列表:
test\cmp_state.ini (2, 2008-04-07)
test\db\add_sub_0sh.tdf (2367, 2008-04-06)
test\db\add_sub_vrh.tdf (1892, 2008-04-06)
test\db\test1.(0).cnf.cdb (501, 2008-04-07)
test\db\test1.(0).cnf.hdb (667, 2008-04-07)
test\db\test1.asm.qmsg (1291, 2008-04-07)
test\db\test1.cbx.xml (87, 2008-04-07)
test\db\test1.cmp.cdb (1747, 2008-04-07)
test\db\test1.cmp.hdb (5125, 2008-04-07)
test\db\test1.cmp.logdb (4, 2008-04-07)
test\db\test1.cmp.rdb (16203, 2008-04-07)
test\db\test1.cmp.tdb (571, 2008-04-07)
test\db\test1.cmp0.ddb (36804, 2008-04-07)
test\db\test1.db_info (135, 2008-04-06)
test\db\test1.eco.cdb (140, 2008-04-07)
test\db\test1.eds_overflow (3, 2008-04-06)
test\db\test1.fit.qmsg (25315, 2008-04-07)
test\db\test1.fnsim.cdb (512, 2008-04-07)
test\db\test1.fnsim.hdb (5217, 2008-04-07)
test\db\test1.hier_info (300, 2008-04-07)
test\db\test1.hif (425, 2008-04-07)
test\db\test1.map.cdb (663, 2008-04-07)
test\db\test1.map.hdb (4975, 2008-04-07)
test\db\test1.map.logdb (4, 2008-04-07)
test\db\test1.map.qmsg (2281, 2008-04-07)
test\db\test1.pre_map.cdb (560, 2008-04-07)
test\db\test1.pre_map.hdb (5202, 2008-04-07)
test\db\test1.psp (0, 2008-04-07)
test\db\test1.rtlv.hdb (5199, 2008-04-07)
test\db\test1.rtlv_sg.cdb (529, 2008-04-07)
test\db\test1.rtlv_sg_swap.cdb (157, 2008-04-07)
test\db\test1.sgdiff.cdb (512, 2008-04-07)
test\db\test1.sgdiff.hdb (5199, 2008-04-07)
test\db\test1.signalprobe.cdb (861, 2008-04-07)
test\db\test1.sim.hdb (2326, 2008-04-07)
test\db\test1.sim.qmsg (2820, 2008-04-07)
test\db\test1.sim.rdb (1459, 2008-04-07)
test\db\test1.sim.vwf (4117, 2008-04-07)
test\db\test1.sld_design_entry.sci (134, 2008-04-07)
test\db\test1.sld_design_entry_dsc.sci (134, 2008-04-07)
... ...

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