fft_test
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：891KB
下载次数：61
上传日期：2008-05-10 16:41:29
上 传 者：
fab
说明： 用vhdl编写的FFT的代码,很全,很强大.
(FFT prepared using VHDL code, it is wide, it is powerful.)
文件列表:
fft_test\.recordref (0, 2006-09-05)
fft_test\ad_ram.mif (13824, 2006-09-05)
fft_test\AutoConstraint_fft_test.sdc (173, 2006-09-05)
fft_test\compxlib.cfg (5823, 2006-08-12)
fft_test\device_usage_statistics.html (40697, 2006-08-12)
fft_test\fft.asy (1671, 2006-08-12)
fft_test\fft.ngc (546982, 2006-08-12)
fft_test\fft.sym (2710, 2006-08-12)
fft_test\fft.v (582696, 2006-08-12)
fft_test\fft.veo (2950, 2006-08-12)
fft_test\fft.vhd (744303, 2006-08-12)
fft_test\fft.vho (4005, 2006-08-12)
fft_test\fft.xco (1367, 2006-08-12)
fft_test\fft_flist.txt (138, 2006-08-12)
fft_test\fft_test.fse (0, 2006-09-05)
fft_test\fft_test.htm (336, 2006-09-05)
fft_test\fft_test.ise (314640, 2006-09-06)
fft_test\fft_test.ise_created (0, 2006-09-05)
fft_test\fft_test.map (0, 2006-09-05)
fft_test\fft_test.ncf (334, 2006-09-05)
fft_test\fft_test.ntrc_log (300, 2006-09-05)
fft_test\fft_test.prj (1764, 2006-09-05)
fft_test\fft_test.sap (513, 2006-09-05)
fft_test\fft_test.sdc (0, 2006-09-05)
fft_test\fft_test.srd (26391, 2006-09-05)
fft_test\fft_test.srm (36007, 2006-09-05)
fft_test\fft_test.srs (10221, 2006-09-05)
fft_test\fft_test.tap (763, 2006-09-05)
fft_test\fft_test.ut (392, 2006-08-12)
fft_test\fft_test.v (2100, 2006-09-05)
fft_test\fft_test_compile.tcl (18, 2006-09-05)
fft_test\fft_test_core\fft_test_core.cgp (543, 2006-09-05)
fft_test\fft_test_core\ram.edn (22154, 2006-09-05)
fft_test\fft_test_core\ram.mif (2304, 2006-09-05)
fft_test\fft_test_core\ram.vhd (4504, 2006-09-05)
fft_test\fft_test_core\ram.vho (3352, 2006-09-05)
fft_test\fft_test_core\ram.xco (1408, 2006-09-05)
fft_test\fft_test_core\ram_flist.txt (94, 2006-09-05)
fft_test\fft_test_core\transcript (433, 2008-05-03)
... ...
The following files were generated for 'ram' in directory
D:\Develop\PQS\FPGA\fft_test:
ram.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the module in a Xilinx (R) FPGA.
ram.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
ram.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
ram.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
ram.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
ram_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
ram_readme.txt:
Text file indicating the files generated and how they are used.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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