说明：  基于FPGA设计数字锁相环，提出了一种由微分超前/滞后型检相器构成数字锁相环的Verilog-HDL建模方案
(FPGA-based design of digital phase-locked loop, a by the differential ahead of/lag type seizure constitutes a digital phase-locked loop phase of the Verilog-HDL modeling program)