SIMTUT_TB.VHD
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：13KB
下载次数：13
上传日期：2008-05-19 22:00:01
上 传 者：
changhai1983
说明： 用StateCAD设计一个“串进并出的加法器”状态机，并使用StateCAD测试激励生成器设计测试激励，验证该状态机，掌握完整的StateCAD设计流程.
(StateCAD design with a )
文件列表:
StateCAD_Demo\SIMTUT_TB.HLF (154, 2002-10-26)
StateCAD_Demo\SIMTUT_TB.REG (2212, 2002-10-26)
StateCAD_Demo\SIMTUT_TB.TMP (1393, 2002-10-26)
StateCAD_Demo\SIMTUT_TB.VHD (5765, 2002-10-26)
StateCAD_Demo\TUT.DIA (6861, 2002-10-26)
StateCAD_Demo\TUT.vhd (6875, 2002-10-26)
StateCAD_Demo\TUT_TB.HLF (154, 2002-10-26)
StateCAD_Demo\TUT_TB.REG (2244, 2002-10-26)
StateCAD_Demo\TUT_TB.TMP (1390, 2002-10-26)
StateCAD_Demo\TUT_TB.VHD (5004, 2002-10-26)
StateCAD_Demo\_import.dmo (1803, 2002-10-24)
源文件\SIMTUT_TB.VHD (5765, 2002-10-26)
源文件\TUT.DIA (6861, 2002-10-26)
源文件\TUT.vhd (6875, 2002-10-26)
源文件\TUT_TB.VHD (5004, 2002-10-26)
StateCAD_Demo (0, 2008-01-20)
源文件 (0, 2008-01-20)
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