VGAVGA
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：2050KB
下载次数：42
上传日期：2008-05-23 10:32:18
上 传 者：
leestar
说明： 利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序
(Verilog prepared using the SPARTAN-based XILINX board VGA Interface display program)
文件列表:
VGAVGA\.recordref (0, 2008-05-03)
VGAVGA\AutoConstraint_vga.sdc (168, 2007-11-16)
VGAVGA\AutoConstraint_vga_key.sdc (366, 2008-05-03)
VGAVGA\blk_mem_gen_ds512.pdf (1123608, 2007-11-17)
VGAVGA\blk_mem_gen_release_notes.txt (4791, 2007-11-17)
VGAVGA\buttonte.v (2664, 2008-05-03)
VGAVGA\change.v (1559, 2008-05-03)
VGAVGA\clkdiv.v (387, 2008-05-03)
VGAVGA\device_usage_statistics.html (35830, 2007-11-17)
VGAVGA\key_display.v (572, 2008-05-03)
VGAVGA\results.txt (24, 2007-11-14)
VGAVGA\rpt_vga_areasrr.htm (9308, 2007-11-16)
VGAVGA\rpt_vga_key.areasrr (17955, 2008-05-03)
VGAVGA\rpt_vga_key_areasrr.htm (21038, 2008-05-03)
VGAVGA\save.asy (1043, 2007-11-17)
VGAVGA\save.mif (34464, 2007-11-17)
VGAVGA\save.ngc (13877, 2007-11-17)
VGAVGA\save.sym (1820, 2007-11-17)
VGAVGA\save.v (4736, 2007-11-17)
VGAVGA\save.veo (3080, 2007-11-17)
VGAVGA\save.vhd (5357, 2007-11-17)
VGAVGA\save.vho (3972, 2007-11-17)
VGAVGA\save.xco (1583, 2007-11-13)
VGAVGA\savecon.v (8485, 2008-05-03)
VGAVGA\savecon1.v (1865, 2007-11-14)
VGAVGA\savecontest.xwv (19632, 2007-11-14)
VGAVGA\savecontest.xwv_bak (19632, 2007-11-14)
VGAVGA\savecontest_bencher.prj (69, 2007-11-14)
VGAVGA\save_flist.txt (139, 2007-11-17)
VGAVGA\sendsave.v (990, 2008-05-03)
VGAVGA\stdout.log (1143, 2008-05-03)
VGAVGA\STD_OUTPUT (0, 2007-11-17)
VGAVGA\tmpRTVStore.xwv (605980, 2007-11-14)
VGAVGA\transcript (9362, 2007-11-14)
VGAVGA\traplog.tlg (1161, 2008-05-03)
VGAVGA\vga.cmd_log (33379, 2007-11-16)
VGAVGA\vga.fse (0, 2007-11-16)
VGAVGA\vga.htm (316, 2007-11-16)
VGAVGA\vga.log (207, 2007-11-16)
... ...
The following files were generated for 'save' in directory
D:\Xilinx\basys\huanyizuoyi\VGAVGA:
save.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
save.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
save.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
save.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
save.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
save.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
save.sym:
Please see the core data sheet.
save.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
save.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
save_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
save_readme.txt:
Text file indicating the files generated and how they are used.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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